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| motorola.com/semiconductors m68hc08 microcontrollers mc68hc908jb8/d rev. 2.1, 12/2003 mc68hc908jb8 mc68hc08jb8 technical data mc68HC08JT8 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc908jb8?mc68hc08jb8mc68HC08JT8 ? rev. 2.1 technical data motorola 3 mc68hc908jb8 mc68hc08jb8 mc68HC08JT8 technical data to provide the most up-to-date info rmation, the re vision of our documents on the world wide web will be the most current. your printed copy may be an earlier revision. to veri fy you have the latest information available, refer to: http://motorola.com/semiconductors/ the following revision history table summarizes cha nges contained in this document. for your conven ience, the page number designators have been linked to the appropriate location. motorola and the stylized m logo are registered trademarks of motorola, inc. digitaldna is a trademark of motorola, inc. this product incorporates superflash? technol ogy licensed from sst. ? motorola, inc., 2003 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . revision history technical data mc68hc908jb8mc68h c08jb8mc68HC08JT8 ? rev. 2.1 4 motorola revision history date revision level description page number(s) december 2003 2.1 4.9 rom-resident routines ? removed block erase references for rom-resident routines. 61 9.8.8 usb control register 3 ? clarified bit descriptions for ostall0 and istall0. 149, 150 9.8.11 usb status register 1 ? clarified bit descriptions for txack, txnak, and txstl. 153 section 19. mechanical specifications ? replaced incorrect 44-pin qfp drawing, case 824e to case 824a. 263 february, 2002 2 corrected ptd6 and ptd7: not direct led drive pins. 28, 210, 217 removed incorrect rx1e text from usb control register 1. 146 corrected figure 9-30 for usb module. 159 corrected timer discrepancies throughout section 11. timer interface module (tim) . 177 added table 12-1 . port contro l register bits summary . 201 changed pullup resi stor limits for d? and i/o ports in 18.6 dc electrical characteristics . 256 added mechanical drawing for 20-pin soic package. 266 added appendix a. mc68hc08jb8 ? rom part. 269 added appendix b. mc68HC08JT8 ? low-voltage rom part. 277 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc908jb8mc68hc08jb8mc68HC08JT8 ? rev. 2.1 technical data motorola list of sections 5 technical data ? mc68hc908jb8?mc68hc08jb8?mc68HC08JT8 list of sections section 1. general description . . . . . . . . . . . . . . . . . . . . 27 section 2. memory map . . . . . . . . . . . . . . . . . . . . . . . . . . 39 section 3. random-a ccess memory (ram) . . . . . . . . . . 51 section 4. flash memory . . . . . . . . . . . . . . . . . . . . . . . . 53 section 5. configuration register (config) . . . . . . . . . 65 section 6. central processor unit (cpu) . . . . . . . . . . . . 69 section 7. oscillator (osc ) . . . . . . . . . . . . . . . . . . . . . . . 89 section 8. system integration mo dule (sim) . . . . . . . . . 93 section 9. universal serial bu s module (usb). . . . . . . 117 section 10. monitor rom (mon) . . . . . . . . . . . . . . . . . . 163 section 11. timer interface module (tim) . . . . . . . . . . . 177 section 12. input/output ports (i/o ) . . . . . . . . . . . . . . . 199 section 13. external interrupt (irq ) . . . . . . . . . . . . . . . 219 section 14. keyboard interrupt module (kbi). . . . . . . . 227 section 15. computer operatin g properly (cop) . . . . 237 section 16. low voltage inhibit (l vi) . . . . . . . . . . . . . . 243 section 17. break module (break) . . . . . . . . . . . . . . . 245 section 18. electrical sp ecifications. . . . . . . . . . . . . . . 253 section 19. mechanical specificati ons . . . . . . . . . . . . . 263 section 20. ordering in formation . . . . . . . . . . . . . . . . . 267 appendix a. mc68hc08jb 8. . . . . . . . . . . . . . . . . . . . . . 269 appendix b. mc68hc08jt 8 . . . . . . . . . . . . . . . . . . . . . . 277 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . list of sections technical data mc68hc908jb8mc68h c08jb8mc68HC08JT8 ? rev. 2.1 6 list of sections motorola f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc908jb8mc68hc08jb8mc68HC08JT8 ? rev. 2.1 technical data motorola table of contents 7 technical data ? mc68hc908jb8?mc68hc08jb8?mc68HC08JT8 table of contents section 1. general description 1.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 1.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 1.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 1.4 mcu block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 1.5 pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 1.5.1 power supply pins (v dd , v ss ) . . . . . . . . . . . . . . . . . . . . . . . 34 1.5.2 voltage regulator out (v reg ) . . . . . . . . . . . . . . . . . . . . . . . 34 1.5.3 oscillator pins (osc1 and osc2) . . . . . . . . . . . . . . . . . . . . 35 1.5.4 external reset pin (rst ) . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 1.5.5 external interrupt pins (irq , pte4/d?) . . . . . . . . . . . . . . . . 35 1.5.6 port a input/output (i/o) pins (pta7/kba7 ?pta0/kba0 ). .36 1.5.7 port b (i/o) pins (ptb 7?ptb0) . . . . . . . . . . . . . . . . . . . . . . 36 1.5.8 port c i/o pins (ptc7?p tc0) . . . . . . . . . . . . . . . . . . . . . . . 36 1.5.9 port d i/o pins (ptd7?p td0) . . . . . . . . . . . . . . . . . . . . . . . 36 1.5.10 port e i/o pins (pte 4/d?, pte3/d+, pte2/tch1, pte1/tch0, pte0/tclk). . . . . . . . . . . . . . . . . . . . . . . . 36 section 2. memory map 2.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 2.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 2.3 i/o section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 2.4 monitor rom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . table of contents technical data mc68hc908jb8mc68h c08jb8mc68HC08JT8 ? rev. 2.1 8 table of contents motorola section 3. random-access memory (ram) 3.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 3.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 3.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 section 4. flash memory 4.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 4.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 4.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 4.4 flash control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 4.5 flash block erase operatio n . . . . . . . . . . . . . . . . . . . . . . . . . 56 4.6 flash mass erase operation . . . . . . . . . . . . . . . . . . . . . . . . . 57 4.7 flash program operation. . . . . . . . . . . . . . . . . . . . . . . . . . . .58 4.8 flash protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 4.8.1 flash block protect regi ster . . . . . . . . . . . . . . . . . . . . . . . 60 4.9 rom-resident routines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 4.9.1 variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 4.9.2 erase routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 4.9.3 program routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 4.9.4 verify routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 section 5. configurat ion register (config) 5.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 5.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 5.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . table of contents mc68hc908jb8mc68hc08jb8mc68HC08JT8 ? rev. 2.1 technical data motorola table of contents 9 section 6. central pr ocessor unit (cpu) 6.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 6.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 6.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 6.4 cpu registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 6.4.1 accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 6.4.2 index register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 6.4.3 stack pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 6.4.4 program counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 6.4.5 condition code register . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 6.5 arithmetic/logic unit (alu) . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 6.6 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 6.6.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76 6.6.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77 6.7 cpu during break interrupt s . . . . . . . . . . . . . . . . . . . . . . . . . . 77 6.8 instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 6.9 opcode map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 section 7. oscillator (osc) 7.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89 7.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 7.3 oscillator external connecti ons . . . . . . . . . . . . . . . . . . . . . . . .90 7.4 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 7.4.1 crystal amplifier input pin (osc1). . . . . . . . . . . . . . . . . . . . 91 7.4.2 crystal amplifier out put pin (osc2) . . . . . . . . . . . . . . . . . . 91 7.4.3 oscillator enable signal (simoscen). . . . . . . . . . . . . . . . . 91 7.4.4 external clock source (oscxclk) . . . . . . . . . . . . . . . . . . . 91 7.4.5 oscillator out (oscout). . . . . . . . . . . . . . . . . . . . . . . . . . . 92 7.5 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 7.5.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92 7.5.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92 7.6 oscillator during break mode . . . . . . . . . . . . . . . . . . . . . . . . . . 92 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . table of contents technical data mc68hc908jb8mc68h c08jb8mc68HC08JT8 ? rev. 2.1 10 table of contents motorola section 8. system integration module (sim) 8.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93 8.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 8.3 sim bus clock control and generation . . . . . . . . . . . . . . . . . . 96 8.3.1 bus timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 8.3.2 clock startup from po r or lvi reset . . . . . . . . . . . . . . . . . 97 8.3.3 clocks in stop mode and wait mode . . . . . . . . . . . . . . . . . . 97 8.4 reset and system initializa tion. . . . . . . . . . . . . . . . . . . . . . . . . 97 8.4.1 external pin reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 8.4.2 active resets from inte rnal sources . . . . . . . . . . . . . . . . . . 99 8.4.2.1 power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100 8.4.2.2 computer operati ng properly (cop) rese t. . . . . . . . . . 101 8.4.2.3 illegal opcode reset . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 8.4.2.4 illegal address reset . . . . . . . . . . . . . . . . . . . . . . . . . . .101 8.4.2.5 low-voltage inhibit (lvi) reset . . . . . . . . . . . . . . . . . . . 102 8.4.2.6 universal serial bu s reset . . . . . . . . . . . . . . . . . . . . . . 102 8.4.2.7 registers values after different resets. . . . . . . . . . . . . 102 8.5 sim counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 8.5.1 sim counter during power-on rese t . . . . . . . . . . . . . . . . 103 8.5.2 sim counter during stop mode re covery . . . . . . . . . . . . . 104 8.5.3 sim counter and reset states. . . . . . . . . . . . . . . . . . . . . . 104 8.6 exception control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104 8.6.1 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 8.6.1.1 hardware interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 8.6.1.2 swi instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 8.6.2 interrupt status regist ers. . . . . . . . . . . . . . . . . . . . . . . . . . 108 8.6.2.1 interrupt stat us register 1 . . . . . . . . . . . . . . . . . . . . . . . 109 8.6.3 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 8.6.4 break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 8.6.5 status flag protection in break mode . . . . . . . . . . . . . . . . 110 8.7 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 8.7.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110 8.7.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112 8.8 sim registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . table of contents mc68hc908jb8mc68hc08jb8mc68HC08JT8 ? rev. 2.1 technical data motorola table of contents 11 8.8.1 break status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 8.8.2 reset status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 8.8.3 break flag control regi ster . . . . . . . . . . . . . . . . . . . . . . .116 section 9. universal serial bus module (usb) 9.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117 9.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 9.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 9.4 pin name conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 9.5 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .124 9.5.1 usb protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 9.5.1.1 sync pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 9.5.1.2 packet identifier fiel d . . . . . . . . . . . . . . . . . . . . . . . . . . 127 9.5.1.3 address field (addr) . . . . . . . . . . . . . . . . . . . . . . . . . . 128 9.5.1.4 endpoint field (endp) . . . . . . . . . . . . . . . . . . . . . . . . . . 128 9.5.1.5 cyclic redundancy c heck (crc) . . . . . . . . . . . . . . . . . 128 9.5.1.6 end-of-packet (eop) . . . . . . . . . . . . . . . . . . . . . . . . . . .128 9.5.2 reset signaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 9.5.3 suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 9.5.4 resume after suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 9.5.4.1 host initiated resume . . . . . . . . . . . . . . . . . . . . . . . . . . 131 9.5.4.2 usb reset signalling. . . . . . . . . . . . . . . . . . . . . . . . . . .131 9.5.4.3 remote wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131 9.5.5 low-speed device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 9.6 clock requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 9.7 hardware description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 9.7.1 voltage regulator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 9.7.2 usb transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 9.7.2.1 output driver characteristics . . . . . . . . . . . . . . . . . . . . . 134 9.7.2.2 low speed (1.5 mbps) driver characteristics . . . . . . . . 134 9.7.2.3 receiver data jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 9.7.2.4 data source jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 9.7.2.5 data signal rise and fall time . . . . . . . . . . . . . . . . . . . 136 9.7.3 usb control logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . table of contents technical data mc68hc908jb8mc68h c08jb8mc68HC08JT8 ? rev. 2.1 12 table of contents motorola 9.8 i/o registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 9.8.1 usb address register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 9.8.2 usb interrupt register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . 139 9.8.3 usb interrupt register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . 141 9.8.4 usb interrupt register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . 144 9.8.5 usb control register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 9.8.6 usb control register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 9.8.7 usb control register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 9.8.8 usb control register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 9.8.9 usb control register 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 9.8.10 usb status register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 9.8.11 usb status register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 9.8.12 usb endpoint 0 data r egisters . . . . . . . . . . . . . . . . . . . . . 154 9.8.13 usb endpoint 1 data r egisters . . . . . . . . . . . . . . . . . . . . . 155 9.8.14 usb endpoint 2 data r egisters . . . . . . . . . . . . . . . . . . . . . 156 9.9 usb interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 9.9.1 usb end-of-transaction interrupt . . . . . . . . . . . . . . . . . . . 157 9.9.1.1 receive control endpoi nt 0 . . . . . . . . . . . . . . . . . . . . . . 158 9.9.1.2 transmit control e ndpoint 0 . . . . . . . . . . . . . . . . . . . . . 160 9.9.1.3 transmit endpoi nt 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 9.9.1.4 transmit endpoi nt 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 9.9.1.5 receive endpoint 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 9.9.2 resume interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 9.9.3 end-of-packet interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 section 10. monitor rom (mon) 10.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .163 10.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 10.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 10.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .164 10.4.1 entering monitor mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 10.4.2 baud rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .169 10.4.3 data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 10.4.4 echoing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 10.4.5 break signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . table of contents mc68hc908jb8mc68hc08jb8mc68HC08JT8 ? rev. 2.1 technical data motorola table of contents 13 10.4.6 commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 10.5 security. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 section 11. timer interface module (tim) 11.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .177 11.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 11.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 11.4 pin name conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 11.5 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .179 11.5.1 tim counter prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 11.5.2 input capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 11.5.3 output compare. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 11.5.3.1 unbuffered output compare . . . . . . . . . . . . . . . . . . . . . 182 11.5.3.2 buffered output com pare . . . . . . . . . . . . . . . . . . . . . . .183 11.5.4 pulse width modulatio n (pwm) . . . . . . . . . . . . . . . . . . . . . 183 11.5.4.1 unbuffered pwm sig nal generation . . . . . . . . . . . . . . . 184 11.5.4.2 buffered pwm signal generation . . . . . . . . . . . . . . . . . 185 11.5.4.3 pwm initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 11.6 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .187 11.7 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 11.7.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .188 11.7.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .188 11.8 tim during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . 188 11.9 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 11.9.1 tim clock pin (pte0/tc lk) . . . . . . . . . . . . . . . . . . . . . . .189 11.9.2 tim channel i/o pins (pte1/tch0:pte2/ tch1) . . . . . . . 189 11.10 i/o registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 11.10.1 tim status and control register . . . . . . . . . . . . . . . . . . . . 190 11.10.2 tim counter registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 11.10.3 tim counter modulo r egisters . . . . . . . . . . . . . . . . . . . . . 193 11.10.4 tim channel status and control registers . . . . . . . . . . . . 194 11.10.5 tim channel registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . table of contents technical data mc68hc908jb8mc68h c08jb8mc68HC08JT8 ? rev. 2.1 14 table of contents motorola section 12. input/output ports (i/o) 12.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .199 12.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 12.3 port a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 12.3.1 port a data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 12.3.2 data direction register a. . . . . . . . . . . . . . . . . . . . . . . . . . 203 12.4 port b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 12.4.1 port b data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 12.4.2 data direction register b. . . . . . . . . . . . . . . . . . . . . . . . . . 205 12.5 port c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 12.5.1 port c data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 12.5.2 data direction register c. . . . . . . . . . . . . . . . . . . . . . . . . . 208 12.6 port d . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 12.6.1 port d data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 12.6.2 data direction register d. . . . . . . . . . . . . . . . . . . . . . . . . . 211 12.7 port e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 12.7.1 port e data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 12.7.2 data direction register e. . . . . . . . . . . . . . . . . . . . . . . . . . 215 12.8 port options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 12.8.1 port option control register . . . . . . . . . . . . . . . . . . . . . . .217 section 13. external interrupt (irq) 13.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .219 13.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 13.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 13.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .220 13.5 irq pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 13.6 pte4/d? pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 13.7 irq module during break interrupts . . . . . . . . . . . . . . . . . . . 223 13.8 irq status and control register . . . . . . . . . . . . . . . . . . . . . . 224 13.9 irq option control regist er. . . . . . . . . . . . . . . . . . . . . . . . . . 225 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . table of contents mc68hc908jb8mc68hc08jb8mc68HC08JT8 ? rev. 2.1 technical data motorola table of contents 15 section 14. keyboard in terrupt module (kbi) 14.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .227 14.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 14.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 14.4 pin name conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 14.5 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .230 14.6 keyboard initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 14.7 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 14.7.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .232 14.7.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .232 14.8 keyboard module during break interrupts . . . . . . . . . . . . . . . 233 14.9 i/o registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 14.9.1 keyboard status and control register. . . . . . . . . . . . . . . . 233 14.9.2 keyboard interrupt enable register . . . . . . . . . . . . . . . . . . 235 section 15. computer op erating properly (cop) 15.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .237 15.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 15.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .238 15.4 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 15.4.1 oscxclk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .239 15.4.2 stop instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 15.4.3 copctl write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .239 15.4.4 power-on reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 15.4.5 internal reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 15.4.6 reset vector fetch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 15.4.7 copd (cop disable). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 15.4.8 coprs (cop rate sele ct) . . . . . . . . . . . . . . . . . . . . . . . . 240 15.5 cop control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 15.6 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .241 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . table of contents technical data mc68hc908jb8mc68h c08jb8mc68HC08JT8 ? rev. 2.1 16 table of contents motorola 15.7 monitor mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .241 15.8 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 15.8.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .242 15.8.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .242 15.9 cop module during break mode . . . . . . . . . . . . . . . . . . . . . . 242 section 16. low voltage inhibit (lvi) 16.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .243 16.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 16.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .243 16.4 lvi control register (config) . . . . . . . . . . . . . . . . . . . . . . .244 16.5 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 16.5.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .244 16.5.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .244 section 17. break module (break) 17.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .245 17.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 17.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246 17.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .246 17.4.1 flag protection during break interr upts . . . . . . . . . . . . . . . 248 17.4.2 cpu during break interrupts . . . . . . . . . . . . . . . . . . . . . . .248 17.4.3 tim during break interr upts . . . . . . . . . . . . . . . . . . . . . . . . 248 17.4.4 cop during break interrupts . . . . . . . . . . . . . . . . . . . . . . . 248 17.5 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 17.5.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .248 17.5.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .249 17.6 break module registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 17.6.1 break status and control register. . . . . . . . . . . . . . . . . . . 249 17.6.2 break address register s . . . . . . . . . . . . . . . . . . . . . . . . . . 250 17.6.3 break status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 17.6.4 break flag control register (bfcr) . . . . . . . . . . . . . . . . . 252 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . table of contents mc68hc908jb8mc68hc08jb8mc68HC08JT8 ? rev. 2.1 technical data motorola table of contents 17 section 18. electrical specifications 18.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .253 18.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253 18.3 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . 254 18.4 functional operating range. . . . . . . . . . . . . . . . . . . . . . . . . . 255 18.5 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255 18.6 dc electrical characterist ics . . . . . . . . . . . . . . . . . . . . . . . . . 256 18.7 control timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257 18.8 oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257 18.9 usb dc electrical charac teristics . . . . . . . . . . . . . . . . . . . . . 258 18.10 usb low-speed source electrical characteri stics . . . . . . . . 259 18.11 usb signaling levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260 18.12 timer interface module characterist ics . . . . . . . . . . . . . . . . . 260 18.13 memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 section 19. mechanic al specifications 19.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .263 19.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 19.3 44-pin plastic quad flat pack (qfp) . . . . . . . . . . . . . . . . . . . 264 19.4 28-pin small outline in tegrated circuit (soic) . . . . . . . . . . . 265 19.5 20-pin dual in-line pa ckage (pdip) . . . . . . . . . . . . . . . . . . . 265 19.6 20-pin small outline in tegrated circuit (soic) . . . . . . . . . . . 266 section 20. ordering information 20.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .267 20.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267 20.3 mc order numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . table of contents technical data mc68hc908jb8mc68h c08jb8mc68HC08JT8 ? rev. 2.1 18 table of contents motorola appendix a. mc68hc08jb8 a.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .269 a.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270 a.3 mcu block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270 a.4 memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270 a.5 reserved registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273 a.6 monitor rom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .273 a.7 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273 a.7.1 dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . .274 a.7.2 memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 275 a.8 mc68hc08jb8 order numb ers . . . . . . . . . . . . . . . . . . . . . . . 275 appendix b. mc68HC08JT8 b.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .277 b.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278 b.3 mcu block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278 b.4 memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278 b.5 power supply pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281 b.6 reserved register bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281 b.7 reserved registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281 b.8 monitor rom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .282 b.9 universal serial bus module. . . . . . . . . . . . . . . . . . . . . . . . . . 282 b.10 low-voltage inhibit module . . . . . . . . . . . . . . . . . . . . . . . . . . 282 b.11 electrical specific ations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282 b.11.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . 282 b.11.2 functional operating range . . . . . . . . . . . . . . . . . . . . . . .283 b.11.3 dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . .283 b.11.4 control timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284 b.11.5 memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 284 b.12 mc68HC08JT8 order number s . . . . . . . . . . . . . . . . . . . . . . . 284 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc908jb8mc68hc08jb8mc68HC08JT8 ? rev. 2.1 technical data motorola list of figures 19 technical data ? mc68hc908jb8?mc68hc08jb8?mc68HC08JT8 list of figures figure title page 1-1 mcu block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 1-2 44-pin qfp pin assi gnments . . . . . . . . . . . . . . . . . . . . . . . . . . 32 1-3 28-pin soic pin assignm ents . . . . . . . . . . . . . . . . . . . . . . . . . 33 1-4 20-pin pdip and soic pin assignments . . . . . . . . . . . . . . . . . 33 1-5 power supply bypassing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 1-6 regulator supply capacit or configuration . . . . . . . . . . . . . . . . 35 2-1 memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 2-2 control, status, and data registers . . . . . . . . . . . . . . . . . . . . .42 4-1 flash memory register summary . . . . . . . . . . . . . . . . . . . . .54 4-2 flash control regist er (flcr) . . . . . . . . . . . . . . . . . . . . . . . 55 4-3 flash programming flowchart . . . . . . . . . . . . . . . . . . . . . . . . 59 4-4 flash block protect register (flbpr). . . . . . . . . . . . . . . . . . 60 4-5 flash block protec t start address . . . . . . . . . . . . . . . . . . . . .60 5-1 configuration register (config). . . . . . . . . . . . . . . . . . . . . . . 66 6-1 cpu registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 6-2 accumulator (a) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 6-3 index register (h:x) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 6-4 stack pointer (sp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 6-5 program counter (pc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 6-6 condition code register (ccr) . . . . . . . . . . . . . . . . . . . . . . . . 74 7-1 oscillator external connecti ons . . . . . . . . . . . . . . . . . . . . . . . .90 8-1 sim block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 8-2 sim i/o register summary. . . . . . . . . . . . . . . . . . . . . . . . . . . .96 8-3 sim clock signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . list of figures technical data mc68hc908jb8mc68h c08jb8mc68HC08JT8 ? rev. 2.1 20 list of figures motorola figure title page 8-4 external reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98 8-5 internal reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 8-6 sources of internal reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 8-7 por recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 8-8 interrupt processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 8-9 interrupt entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 8-10 interrupt recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 8-11 interrupt recognition example . . . . . . . . . . . . . . . . . . . . . . . . 107 8-12 interrupt status register 1 (int1). . . . . . . . . . . . . . . . . . . . . . 109 8-13 wait mode entry timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 8-14 wait recovery from interrupt or br eak . . . . . . . . . . . . . . . . . . 111 8-15 wait recovery from internal reset. . . . . . . . . . . . . . . . . . . . . 111 8-16 stop mode entry timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 8-17 stop mode recovery fr om interrupt or break . . . . . . . . . . . . . 113 8-18 break status register (b sr) . . . . . . . . . . . . . . . . . . . . . . . . . 113 8-19 reset status register (rsr) . . . . . . . . . . . . . . . . . . . . . . . . . 115 8-20 break flag control register (bfcr) . . . . . . . . . . . . . . . . . . . 116 9-1 usb i/o register summar y . . . . . . . . . . . . . . . . . . . . . . . . . . 120 9-2 usb block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 9-3 supported transaction types per en dpoint. . . . . . . . . . . . . . 125 9-4 supported usb packet types . . . . . . . . . . . . . . . . . . . . . . . . 126 9-5 sync pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 9-6 sop, sync signaling, and voltage lev els . . . . . . . . . . . . . . . 127 9-7 eop transaction voltage levels . . . . . . . . . . . . . . . . . . . . . . 129 9-8 eop width timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 9-9 external low-speed device configurat ion . . . . . . . . . . . . . . . 132 9-10 regulator electrical connections . . . . . . . . . . . . . . . . . . . . . . 133 9-11 receiver characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 9-12 differential input sensitivity range. . . . . . . . . . . . . . . . . . . . . 135 9-13 data jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 9-14 data signal rise and fall time . . . . . . . . . . . . . . . . . . . . . . .136 9-15 usb address register ( uaddr) . . . . . . . . . . . . . . . . . . . . . . 138 9-16 usb interrupt register 0 (uir0) . . . . . . . . . . . . . . . . . . . . . . . 139 9-17 usb interrupt register 1 (uir1) . . . . . . . . . . . . . . . . . . . . . . . 141 9-18 usb interrupt register 2 (uir2) . . . . . . . . . . . . . . . . . . . . . . . 144 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . list of figures mc68hc908jb8mc68hc08jb8mc68HC08JT8 ? rev. 2.1 technical data motorola list of figures 21 figure title page 9-19 usb control register 0 (ucr0) . . . . . . . . . . . . . . . . . . . . . . . 145 9-20 usb control register 1 (ucr1) . . . . . . . . . . . . . . . . . . . . . . . 146 9-21 usb control register 2 (ucr2) . . . . . . . . . . . . . . . . . . . . . . . 147 9-22 usb control register 3 (ucr3) . . . . . . . . . . . . . . . . . . . . . . . 149 9-23 usb control register 4 (ucr4) . . . . . . . . . . . . . . . . . . . . . . . 151 9-24 usb status register 0 (usr0). . . . . . . . . . . . . . . . . . . . . . . . 152 9-25 usb status register 1 (usr1). . . . . . . . . . . . . . . . . . . . . . . . 153 9-26 usb endpoint 0 data registers (ue0d0?ue0d7 ). . . . . . . . . 154 9-27 usb endpoint 1 data registers (ue1d0?ue1d7 ). . . . . . . . . 155 9-28 usb endpoint 2 data registers (ue2d0?ue2d7 ). . . . . . . . . 156 9-29 out token data flow for receive endpoint 0. . . . . . . . . . . . 158 9-30 setup token data flow for receiv e endpoint 0 . . . . . . . . . 159 9-31 in token data flow for transmit endpoint 0 . . . . . . . . . . . . . 160 9-32 in token data flow for transmit endpoint 1 . . . . . . . . . . . . . 161 10-1 monitor mode circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 10-2 low-voltage monitor m ode entry flowchart. . . . . . . . . . . . . . 168 10-3 monitor data format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 10-4 sample monitor waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . 170 10-5 read transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .170 10-6 break transaction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .171 10-7 monitor mode entry timing . . . . . . . . . . . . . . . . . . . . . . . . . . .175 11-1 tim block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 11-2 tim i/o register summary . . . . . . . . . . . . . . . . . . . . . . . . . . .180 11-3 pwm period and pulse wi dth . . . . . . . . . . . . . . . . . . . . . . . . 184 11-4 tim status and control register (tsc ) . . . . . . . . . . . . . . . . . 190 11-5 tim counter register s (tcnth:tcntl) . . . . . . . . . . . . . . . . 192 11-6 tim counter modulo registers (tmodh:tmodl) . . . . . . . . . 193 11-7 tim channel status and contro l registers (tsc0:tsc1) . . . 194 11-8 chxmax latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .197 11-9 tim channel registers (tch0h/l:t ch1h/l). . . . . . . . . . . . . 198 12-1 i/o port register summary. . . . . . . . . . . . . . . . . . . . . . . . . . .200 12-2 port a data register (pta ) . . . . . . . . . . . . . . . . . . . . . . . . . . 202 12-3 data direction register a (ddra) . . . . . . . . . . . . . . . . . . . . . 203 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . list of figures technical data mc68hc908jb8mc68h c08jb8mc68HC08JT8 ? rev. 2.1 22 list of figures motorola 12-4 port a i/o circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 12-5 port b data register (ptb ) . . . . . . . . . . . . . . . . . . . . . . . . . . 204 12-6 data direction register b (ddrb) . . . . . . . . . . . . . . . . . . . . . 205 12-7 port b i/o circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 12-8 port c data register (ptc ) . . . . . . . . . . . . . . . . . . . . . . . . . . 207 12-9 data direction register c (ddrc) . . . . . . . . . . . . . . . . . . . . . 208 12-10 port c i/o circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 12-11 port d data register (ptd ) . . . . . . . . . . . . . . . . . . . . . . . . . . 210 12-12 data direction register d (ddrd) . . . . . . . . . . . . . . . . . . . . . 211 12-13 port d i/o circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 12-14 port e data register (pte ) . . . . . . . . . . . . . . . . . . . . . . . . . . 213 12-15 data direction register e (ddre) . . . . . . . . . . . . . . . . . . . . . 215 12-16 port e i/o circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 12-17 port option control regi ster (pocr). . . . . . . . . . . . . . . . . . . 217 13-1 irq module block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 221 13-2 irq i/o register summary. . . . . . . . . . . . . . . . . . . . . . . . . . .221 13-3 irq status and control register (iscr) . . . . . . . . . . . . . . . . 224 13-4 irq option control regist er (iocr) . . . . . . . . . . . . . . . . . . . 225 14-1 keyboard module block di agram . . . . . . . . . . . . . . . . . . . . . . 229 14-2 keyboard status and control register (kbscr) . . . . . . . . . . 234 14-3 keyboard interrupt enable register (kbier) . . . . . . . . . . . . . 235 15-1 cop block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238 15-2 configuration register (config). . . . . . . . . . . . . . . . . . . . . . 240 15-3 cop control register (copctl) . . . . . . . . . . . . . . . . . . . . . . 241 16-1 lvi module block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . .244 16-2 configuration register (config). . . . . . . . . . . . . . . . . . . . . . 244 17-1 break module block diagram . . . . . . . . . . . . . . . . . . . . . . . . . 247 17-2 break i/o register summ ary . . . . . . . . . . . . . . . . . . . . . . . . . 247 17-3 break status and control register (brkscr). . . . . . . . . . . . 249 17-4 break address register high (brkh) . . . . . . . . . . . . . . . . . . 250 17-5 break address register low (brkl) . . . . . . . . . . . . . . . . . . . 250 17-6 break status register (b sr) . . . . . . . . . . . . . . . . . . . . . . . . . 251 17-7 break flag control register high (b fcr) . . . . . . . . . . . . . . . 252 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . list of figures mc68hc908jb8mc68hc08jb8mc68HC08JT8 ? rev. 2.1 technical data motorola list of figures 23 figure title page 19-1 44-pin qfp (case #824e) . . . . . . . . . . . . . . . . . . . . . . . . . . . 264 19-2 28-pin soic (case #751f). . . . . . . . . . . . . . . . . . . . . . . . . . .265 19-3 20-pin pdip (case #738) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265 19-4 20-pin soic (case #751d) . . . . . . . . . . . . . . . . . . . . . . . . . . 266 a-1 mc68hc08jb8 block diagram . . . . . . . . . . . . . . . . . . . . . . . 271 a-2 mc68hc08jb8 memory map. . . . . . . . . . . . . . . . . . . . . . . . . 272 b-1 mc68HC08JT8 block di agram . . . . . . . . . . . . . . . . . . . . . . .279 b-2 mc68HC08JT8 memory map . . . . . . . . . . . . . . . . . . . . . . . . . 280 b-3 power supply bypassing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . list of figures technical data mc68hc908jb8mc68h c08jb8mc68HC08JT8 ? rev. 2.1 24 list of figures motorola f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc908jb8mc68hc08jb8mc68HC08JT8 ? rev. 2.1 technical data motorola list of tables 25 technical data ? mc68hc908jb8?mc68hc08jb8?mc68HC08JT8 list of tables table title page 1-1 summary of pin fu nctions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 2-1 vector addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 4-1 rom-resident routines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 4-2 rom-resident routine vari ables. . . . . . . . . . . . . . . . . . . . . . . 62 4-3 erase routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 4-4 program routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 4-5 verify routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 6-1 instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 6-2 opcode map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 8-1 sim module signal name conventions . . . . . . . . . . . . . . . . . . 95 8-2 pin bit set timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 8-3 registers not affected by normal re set. . . . . . . . . . . . . . . . . 103 8-4 interrupt sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 9-1 usb module pin name c onventions . . . . . . . . . . . . . . . . . . . 120 9-2 supported packet ident ifiers. . . . . . . . . . . . . . . . . . . . . . . . . . 127 10-1 mode entry requirements and options . . . . . . . . . . . . . . . . . 166 10-2 monitor mode vector diffe rences . . . . . . . . . . . . . . . . . . . . . . 169 10-3 monitor baud rate selection . . . . . . . . . . . . . . . . . . . . . . . . . 169 10-4 read (read memory) command . . . . . . . . . . . . . . . . . . . . . 172 10-5 write (write memory) command. . . . . . . . . . . . . . . . . . . . . 172 10-6 iread (indexed read) co mmand . . . . . . . . . . . . . . . . . . . . . 173 10-7 iwrite (indexed write) command . . . . . . . . . . . . . . . . . . . . 173 10-8 readsp (read stack po inter) command . . . . . . . . . . . . . . . 174 10-9 run (run user program) command . . . . . . . . . . . . . . . . . . . 174 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . list of tables technical data mc68hc908jb8mc68h c08jb8mc68HC08JT8 ? rev. 2.1 26 list of tables motorola 11-1 tim pin name conventions . . . . . . . . . . . . . . . . . . . . . . . . . . 178 11-2 prescaler selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 11-3 mode, edge, and level selection . . . . . . . . . . . . . . . . . . . . . . 196 12-1 port control register bits summary. . . . . . . . . . . . . . . . . . . .201 12-2 port a pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 12-3 port b pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 12-4 port c pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 12-5 port d pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 12-6 port e pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 14-1 kbi pin name conventions . . . . . . . . . . . . . . . . . . . . . . . . . . 228 14-2 i/o register summar y . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .229 20-1 mc order numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267 a-1 summary of mc68h c08jb8 and mc68hc908jb8 differences. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270 a-2 mc68hc08jb8 order numb ers . . . . . . . . . . . . . . . . . . . . . . . 275 b-1 summary of mc68h c08jt8 and mc68hc908jb8 differences. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278 b-2 mc68HC08JT8 order numbers . . . . . . . . . . . . . . . . . . . . . . . 284 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc908jb8mc68hc08jb8mc68HC08JT8 ? rev. 2.1 technical data motorola general description 27 technical data ? mc68hc908jb8?mc68hc08jb8?mc68HC08JT8 section 1. general description 1.1 contents 1.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 1.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 1.4 mcu block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 1.5 pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 1.5.1 power supply pins (v dd , v ss ) . . . . . . . . . . . . . . . . . . . . . . . 34 1.5.2 voltage regulator out (v reg ) . . . . . . . . . . . . . . . . . . . . . . . 34 1.5.3 oscillator pins (osc1 and osc2) . . . . . . . . . . . . . . . . . . . . 35 1.5.4 external reset pin (rst ) . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 1.5.5 external interrupt pins (irq , pte4/d?) . . . . . . . . . . . . . . . . 35 1.5.6 port a input/output (i/o) pins (pta7/kba7 ?pta0/kba0 ). .36 1.5.7 port b (i/o) pins (ptb 7?ptb0) . . . . . . . . . . . . . . . . . . . . . . 36 1.5.8 port c i/o pins (ptc7?p tc0) . . . . . . . . . . . . . . . . . . . . . . . 36 1.5.9 port d i/o pins (ptd7?p td0) . . . . . . . . . . . . . . . . . . . . . . . 36 1.5.10 port e i/o pins (pte 4/d?, pte3/d+, pte2/tch1, pte1/tch0, pte0/tclk). . . . . . . . . . . . . . . . . . . . . . . . 36 1.2 introduction the mc68hc908jb8 is a member of the low- cost, high-performance m68hc08 family of 8-bi t microcontroller units (mcus). the m68hc08 family is based on the customer-spec ified integrated circuit (csic) design strategy. all mcus in t he family use the enhanced m68hc08 central processor unit (cpu08) and are available with a variety of modules, memory sizes and types, and package types. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . general description technical data mc68hc908jb8mc68h c08jb8mc68HC08JT8 ? rev. 2.1 28 general description motorola 1.3 features features of the mc 68hc908jb8 include: high-performance m68hc08 architecture fully upward-compatible objec t code with m6805, m146805, and m68hc05 families 3-mhz internal bus frequency 8,192 bytes of on -chip flash memory 256 bytes of on-chip r andom-access memory (ram) flash program memory security 1 on-chip programming firmware for use with host pc computer up to 37 general-purpose 3.3v i nput/output (i/o) pins, including: ? 13 or 10 shared-function i/ o pins, depending on package ? 24, 8, or 2 dedicated i/o pins, depending on package ? 8 keyboard interrupts on port a, on all packages ? 10ma sink capability for normal led on 4 pins ? 25ma sink capability fo r infrared led on 2 pins ? 10ma sink capability for ps/2 connection on 2 pins (with usb module disabled) 16-bit, 2-channel timer interfac e module (tim) with selectable input capture, output compare, pwm capability on each channel, and external clock input option (tclk) full universal serial bus specif ication 1.1 low-speed functions: ? 1.5 mbps data rate ? on-chip 3.3v regulator ? endpoint 0 with 8-byte transmit buffer and 8-byte receive buffer ? endpoint 1 with 8-byte transmit buffer ? endpoint 2 with 8-byte transmit buffer and 8-byte receive buffer 1. no security feature is absolutely secure. howe ver, motorola?s strategy is to make reading or copying the flash difficul t for unauthorized users. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . general description features mc68hc908jb8mc68hc08jb8mc68HC08JT8 ? rev. 2.1 technical data motorola general description 29 system protection features: ? optional computer operati ng properly (cop) reset ? optional low-voltage detection with reset ? illegal opcode detection with reset ? illegal address detection with reset low-power design (fully stat ic with stop and wait modes) master reset pin with internal pullup and power-on reset external interrupt pin with prog rammable internal pullup (irq ) 44-pin quad flat pack (qfp), 28-pin small outline integrated circuit package (soic), 20-pin small out line integrated circuit package (soic), and 20-pin plastic dual in-line package (dip) specific features of mc 68hc908jb8 in 44-pin are: ? port b is 8 bits: ptb0?ptb7 ? port c is 8 bits: ptc0?ptc7 ? port d is 8 bits: ptd0?ptd7 ? port e is 5 bits: pte0?pte4; 2-channel tim m odule with tclk input option specific features of mc 68hc908jb8 in 28-pin are: ? port b is not available ? port c is only one bit: ptc0 ? port d is only 7 bits: ptd0?ptd6 ? port e is 5 bits: pte0?pte4; 2-channel tim m odule with tclk input option specific features of mc 68hc908jb8 in 20-pin are: ? port b is not available ? port c is only one bit: ptc0 ? port d is only one bit: ptd0/1 ; internal ptd0 and ptd1 pads are bonded together to a single pin, ptd0/1 ? port e is only 3 bits: pte1, pte3, and pte4; 1-channel tim modul e without tclk input option f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . general description technical data mc68hc908jb8mc68h c08jb8mc68HC08JT8 ? rev. 2.1 30 general description motorola features of the cpu08 include the following: enhanced hc05 programming model extensive loop control functions 16 addressing modes (eight more than the hc05) 16-bit index register and stack pointer memory-to-memory data transfers fast 8 8 multiply instruction fast 16/8 divide instruction binary-coded decimal (bcd) instructions optimization for controller applications efficient c language support 1.4 mcu block diagram figure 1-1 shows the structure of the mc68hc908jb8. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc908jb8mc68hc08jb8mc68HC08JT8 ? rev. 2.1 technical data motorola general description 31 general description mcu block diagram figure 1-1. mcu block diagram system integration module timer interface module low voltage inhibit module computer operating properly module arithmetic/logic unit (alu) cpu registers m68hc08 cpu control and status registers ? 64 bytes user flash memory ? 8,192 bytes user ram ? 256 bytes monitor rom ? 976 bytes user flash vectors ? 16 bytes irq module power pta ddra ddre pte internal bus osc1 osc2 (1), (2) rst (1), (3) irq v dd v ss pta7/kba7 (3) pte4/d? (3) (4) (5) pte3/d+ (3) (4) (5) pte2/tch1 (3) pte1/tch0 (3) pte0/tclk (3) ptb ddrb ptb7?ptb0 (3) ptd ddrd ptd5?ptd2 (4) (5) usb module usb endpoint 0, 1, 2 internal voltage regulator v reg (3.3 v) (1) pins have 5v logic. (2) pins have integrated pullup device. (3) pins have software configurable pullup device. (4) pins are open-drain when configured as output. (5) pins have 10ma sink capability. (6) pins have 25ma sink capability. ls usb transceiver break module oscillator ptc ddrc ptc7?ptc0 (3) keyboard interrupt module power-on reset module ptd7?ptd6 (4) ptd1?ptd0 (4) (6) pta0/kba0 (3) : f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . general description technical data mc68hc908jb8?mc68h c08jb8mc68HC08JT8 ? rev. 2.1 32 general description motorola 1.5 pin assignments figure 1-2. 44-pin qfp pin assignments 1 2 3 4 5 6 7 8 9 10 11 33 32 31 30 29 28 27 26 25 24 23 44 43 42 41 40 39 38 37 36 35 34 12 13 14 15 16 17 18 19 20 21 22 pta2/kba2 osc2 osc1 v ss ptb3 ptb4 ptb5 ptb6 ptb7 rst pta0/kba0 pta1/kba1 pta7/kba7 pta3/kba3 ptc7 ptc6 ptc5 ptc4 pte0/tclk pte2/tch1 pta4/kba4 pta5/kba5 pta6/kba6 pte3/d+ pte4/d? ptc0 ptc1 ptc2 ptc3 irq ptd5 v reg v dd ptb2 ptb1 ptd1 ptd2 ptd3 ptb0 ptd0 ptd4 pte1/tch0 ptd7 ptd6 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . general description pin assignments mc68hc908jb8mc68hc08jb8mc68HC08JT8 ? rev. 2.1 technical data motorola general description 33 figure 1-3. 28-pin soic pin assignments figure 1-4. 20-pin pdip and soic pin assignments note: in 20-pin package, the ptd0 and ptd1 internal pads are bonded together to ptd0/1 pin. 1 2 3 4 5 6 7 28 27 26 25 24 23 22 21 20 19 18 12 13 14 17 16 15 8 9 10 11 osc1 irq pta0/kba0 rst pta1/kba1 pta2/kba2 pta3/kba3 pte0/tclk pte2/tch1 pta4/kba4 pta5/kba5 pta6/kba6 pta7/kba7 ptd5 ptd6 osc2 v reg v dd ptd0 ptd1 ptd2 ptd3 ptd4 pte1/tch0 pte3/d+ pte4/d? ptc0 v ss pins not available on 28-pin package: ptb0 ptb1 ptc1 ptb2 ptc2 ptb3 ptc3 ptb4 ptc4 ptb5 ptc5 ptb6 ptc6 ptb7 ptc7 ptd7 internal pads are unconnected. 1 2 3 4 5 6 7 20 19 18 17 16 15 14 13 12 11 8 9 10 osc1 pta0/kba0 rst pta1/kba1 pta2/kba2 pta3/kba3 pta4/kba4 pta5/kba5 pta6/kba6 pta7/kba7 irq osc2 v reg v dd ptd0/1 pte1/tch0 pte3/d+ pte4/d? ptc0 v ss ptd0/1 pin: ptd0 and ptd1 internal pads are bonded together to ptd0/1 pin. pins not available on 20-pin package: ptb0 pte0/tclk ptb1 ptc1 ptb2 ptc2 ptd2 pte2/tch1 ptb3 ptc3 ptd3 ptb4 ptc4 ptd4 ptb5 ptc5 ptd5 ptb6 ptc6 ptd6 ptb7 ptc7 ptd7 internal pads are unconnected. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . general description technical data mc68hc908jb8mc68h c08jb8mc68HC08JT8 ? rev. 2.1 34 general description motorola 1.5.1 power supply pins (v dd , v ss ) v dd and v ss are the power supply and ground pins. the mcu operates from a single power supply. fast signal transitions on mcu pins place high, short-duration current demands on the power supply. to preven t noise problems, take special care to provide power suppl y bypassing at the mcu as figure 1-5 shows. place the bypass capacitors as close to the mcu power pins as possible. use high-frequency-res ponse ceramic capacitors for c bypass . c bulk are optional bulk current bypass capacitors for use in applications that require the port pins to source high current levels. figure 1-5. power supply bypassing 1.5.2 voltage regulator out (v reg ) v reg is the 3.3 v output of the on-chip voltage regulator. v reg is used internally for the mcu oper ation and the usb data driv er. it is also used to supply the volt age for the external pullup re sistor required on the usb?s d? line. the v reg pin requires an exte rnal bulk capacitor 4.7 f or larger and a 0.1 f ceramic bypass capacitor as figure 1-6 shows. place the bypass capacitor s as close to the v reg pin as possible. mcu c bulk c bypass 0.1 f + note: values shown are typical values. v dd v dd v ss f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . general description pin assignments mc68hc908jb8mc68hc08jb8mc68HC08JT8 ? rev. 2.1 technical data motorola general description 35 figure 1-6. regulator s upply capacitor configuration 1.5.3 oscillator pins (osc1 and osc2) the osc1 and osc2 pins ar e the connections for the on-chip oscillator circuit. 1.5.4 external reset pin (rst ) a logic zero on the rst pin forces the mcu to a known start-up state. rst is bidirectional, allowin g a reset of the entire system. it is driven low when any internal reset s ource is asserted. the rst pin contains an internal pullup device to v dd . (see section 8. system integration module (sim) .) 1.5.5 external interrupt pins (irq , pte4/d?) irq is an asynchronous exter nal interrupt pin. irq is also the pin to enter monitor mode. the irq pin contains a softwa re configurable pullup device to v dd . pte4/d? can be programmed to trigger the irq interrupt. (see section 13. exter nal interrupt (irq) .) mcu v reg c regbulk c regbypass 0.1 f v ss + v reg > 4.7 f f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . general description technical data mc68hc908jb8mc68h c08jb8mc68HC08JT8 ? rev. 2.1 36 general description motorola 1.5.6 port a input/output (i/o) pins (pta7/kba7 ?pta0/kba0 ) pta7/kba7 ?pta0/kba0 are general-purpose bidirectional i/o port pins. (see section 12. input/o utput ports (i/o) .) each pin contains a software configurabl e pullup device to v reg when the pin is configured as an input. (see 12.8 port options .) each pin can also be programmed as an external keyboard interrupt pin. (see section 14. keyboard interrupt module (kbi) .) 1.5.7 port b (i/o) pins (ptb7?ptb0) ptb7?ptb0 are general-purpose bidire ctional i/o port pins. each pin contains a software conf igurable pullup device to v reg when the pin is configured as an input. (see 12.8 port options .) 1.5.8 port c i/o pins (ptc7?ptc0) ptc7?ptc0 are general-purpose bidi rectional i/o port pins. (see section 12. input/ou tput ports (i/o) .) each pin contains a software configurable pullup device to v reg when the pin is configured as an input. (see 12.8 port options .) 1.5.9 port d i/o pins (ptd7?ptd0) ptd7?ptd0 are general-purpose bidire ctional i/o port pins; open-drain when configured as output. (see section 12. input/output ports (i/o) .) ptd5?ptd2 are software configurable to be 10ma sink pins for direct led connections. ptd1?ptd0 are so ftware configurable to be 25ma sink pins for direct in frared led connec tions. (see 12.8 port options .) 1.5.10 port e i/o pins (pte4/d?, pte3/d+, pte2/tch1, pte1/tch0, pte0/tclk) port e is a 5-bit special function port that shares two of its pins with the usb module and three of its pins with the timer interface module. each pte2?pte0 pin contains a so ftware configurable pullup device to v reg when the pin is configur ed as an input or output. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . general description pin assignments mc68hc908jb8mc68hc08jb8mc68HC08JT8 ? rev. 2.1 technical data motorola general description 37 when the usb module is disabled, the pte4 and pte3 pins are general-purpose bidirectional i/o port pins with 10ma sink capability. each pin is open-dr ain when configured as an output; and each pin contains a software configurable 5k ? pullup to v dd when configured as an input . the pte4 pin can also be enabled to trigger the irq interrupt. when the usb module is enabled, the pte4/d? and pte3/d+ pins become the usb module d? and d+ pins. the d? pin contains a software configurable 1.5k ? pullup to v reg . (see section 11. timer interface module (tim) , section 9. universa l serial bus module (usb) and section 12. input/ou tput ports (i/o) .) summary of the pin func tions are provided in table 1-1 . table 1-1. summary of pin functions pin name pin description in/out voltage level v dd power supply. in 4.0 to 5.5v v ss power supply ground. out 0v v reg regulated 3.3v output from mcu. out v reg (3.3v) rst reset input; active low. with internal pullup to v dd and schmitt trigger input. in/out v dd irq external irq pin; with programmable internal pullup to v dd and schmitt trigger input. in v dd used for mode entry selection. in v reg to v dd +v hi osc1 crystal oscillator input. in v reg osc2 crystal oscillator output; inverting of osc1 signal. out v reg pta0/kba0 : pta7/kba7 8-bit general-purpose i/o port. in/out v reg pins as keyboard interrupts, kba0 ?kba7 .in v reg each pin has programmable internal pullup to v reg when configured as input. in v reg ptb0?ptb7 8-bit general-purpose i/o port. in/out v reg each pin has programmable internal pullup to v reg when configured as input. in v reg f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . general description technical data mc68hc908jb8mc68h c08jb8mc68HC08JT8 ? rev. 2.1 38 general description motorola ptc0?ptc7 8-bit general-purpose i/o port. in/out v reg each pin has programmable internal pullup to v reg when configured as input. in v reg ptd0?ptd7 8-bit general-purpose i/o port; open-drain when configured as output. in out v reg v reg or v dd ptd0?ptd1 have configurable 25ma sink for infrared led. out v reg or v dd ptd2?ptd5 have configurable 10ma sink for led. out v reg or v dd pte0/tclk pte1/tch0 pte2/tch1 pte0?pte2 are general-purpose i/o pins. in/out v reg pte0?pte2 have programmable internal pullup to v reg when configured as input or output. in/out v reg pte0 as tclk of timer interface module. in v reg pte1 as tch0 of timer interface module. in/out v reg pte2 as tch1 of timer interface module. in/out v reg pte3/d+ pte4/d? pte3?pte4 are general-purpose i/o pins; open-drain when configured as output. in out v dd v reg or v dd pte3?pte4 have programmable internal pullup to v dd when configured as input. in v dd pte3 as d+ of usb module. in/out v reg pte4 as d? of usb module. in/out v reg pte4 as additional irq interrupt. in v dd table 1-1. summary of pin functions pin name pin description in/out voltage level f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc908jb8mc68hc08jb8mc68HC08JT8 ? rev. 2.1 technical data motorola memory map 39 technical data ? mc68hc908jb8?mc68hc08jb8?mc68HC08JT8 section 2. memory map 2.1 contents 2.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 2.3 i/o section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 2.4 monitor rom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 2.2 introduction the cpu08 can address 64 kbytes of memory space. the memory map, shown in figure 2-1 , includes: 8,192 bytes of user flash memory 256 bytes of ram 16 bytes of user-defined vectors 976 bytes of monitor rom f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . memory map technical data mc68hc908jb8mc68h c08jb8mc68HC08JT8 ? rev. 2.1 40 memory map motorola $0000 $003f i/o registers 64 bytes $0040 $013f ram 256 bytes $0140 $dbff unimplemented 56,000 bytes $dc00 $fbff flash 8,192 bytes $fc00 $fdff monitor rom 1 512 bytes $fe00 break status register (bsr) $fe01 reset status register (rsr) $fe02 reserved $fe03 break flag control register (bfcr) $fe04 interrupt status register 1 (int1) $fe05 reserved $fe06 reserved $fe07 reserved $fe08 flash control register (flcr) $fe09 flash block protect register (flbpr) $fe0a reserved $fe0b reserved $fe0c break address high register (brkh) $fe0d break address low register (brkl) $fe0e break status and c ontrol register (brkscr) $fe0f reserved $fe10 $ffdf monitor rom 2 464 bytes $ffe0 $ffef reserved 16 bytes $fff0 $ffff flash vectors 16 bytes figure 2-1. memory map f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . memory map i/o section mc68hc908jb8mc68hc08jb8mc68HC08JT8 ? rev. 2.1 technical data motorola memory map 41 2.3 i/o section addresses $0000?$003f, shown in figure 2-2 , contain most of the control, status, and data registers. additional i/o registers have these addresses: $fe00; break stat us register, bsr $fe01; reset status register, rsr $fe02; reserved $fe03; break flag c ontrol register, bfcr $fe04; interrupt stat us register 1, int1 $fe05; reserved $fe06; reserved $fe07; reserved $fe08; flash contro l register, flcr $fe09; flash block protect register, flbpr $fe0a; reserved $fe0b; reserved $fe0c; break address register high, brkh $fe0d; break address register low, brkl $fe0e; break status and control register, brkscr $ffff; cop control register, copctl 2.4 monitor rom the 512 bytes at addresse s $fc00?$fdff and 464 bytes at addresses $fe10?$ffdf are reserv ed rom addresses that contain the instructions for the monitor functions. (see section 10. monitor rom (mon) .) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . memory map technical data mc68hc908jb8mc68h c08jb8mc68HC08JT8 ? rev. 2.1 42 memory map motorola addr.register name bit 7654321bit 0 $0000 port a data register (pta) read: pta7 pta6 pta5 pta4 pta3 pta2 pta1 pta0 write: reset: unaffected by reset $0001 port b data register (ptb) read: ptb7 ptb6 ptb5 ptb4 ptb3 ptb2 ptb1 ptb0 write: reset: unaffected by reset $0002 port c data register (ptc) read: ptc7 ptc6 ptc5 ptc4 ptc3 ptc2 ptc1 ptc0 write: reset: unaffected by reset $0003 port d data register (ptd) read: ptd7 ptd6 ptd5 ptd4 ptd3 ptd2 ptd1 ptd0 write: reset: unaffected by reset $0004 data direction register a (ddra) read: ddra7 ddra6 ddra5 ddra4 ddra3 ddra2 ddra1 ddra0 write: reset:0*0000000 * ddra7 bit is reset by por or lvi reset only. $0005 data direction register b (ddrb) read: ddrb7 ddrb6 ddrb5 ddrb4 ddrb3 ddrb2 ddrb1 ddrb0 write: reset:00000000 $0006 data direction register c (ddrc) read: ddrc7 ddrc6 ddrc5 ddrc4 ddrc3 ddrc2 ddrc1 ddrc0 write: reset:00000000 $0007 data direction register d (ddrd) read: ddrd7 ddrd6 ddrd5 ddrd4 ddrd3 ddrd2 ddrd1 ddrd0 write: reset:00000000 $0008 port e data register (pte) read: 0 0 0 pte4 pte3 pte2 pte1 pte0 write: reset: unaffected by reset $0009 data direction register e (ddre) read: 0 0 0 ddre4 ddre3 ddre2 ddre1 ddre0 write: reset:00000000 = unimplemented r = reserved u = unaffected by reset figure 2-2. control, status, a nd data register s (sheet 1 of 8) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . memory map monitor rom mc68hc908jb8mc68hc08jb8mc68HC08JT8 ? rev. 2.1 technical data motorola memory map 43 $000a tim status and control register (tsc) read: tof toie tstop 00 ps2 ps1 ps0 write: 0 trst reset:00100000 $000b unimplemented read: write: $000c tim counter register high (tcnth) read: bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 write: reset:00000000 $000d tim counter register low (tcntl) read: bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 write: reset:00000000 $000e tim counter modulo register high (tmodh) read: bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 write: reset:11111111 $000f tim counter modulo register low (tmodl) read: bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 write: reset:11111111 $0010 tim channel 0 status and control register (tsc0) read: ch0f ch0ie ms0b ms0a els0b els0a tov0 ch0max write: 0 reset:00000000 $0011 tim channel 0 register high (tch0h) read: bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 write: reset: indeterminate after reset $0012 tim channel 0 register low (tch0l) read: bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 write: reset: indeterminate after reset $0013 tim channel 1 status and control register (tsc1) read: ch1f ch1ie 0 ms1a els1b els1a tov1 ch1max write: 0 reset:00000000 addr.register name bit 7654321bit 0 = unimplemented r = reserved u = unaffected by reset figure 2-2. control, status, a nd data register s (sheet 2 of 8) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . memory map technical data mc68hc908jb8mc68h c08jb8mc68HC08JT8 ? rev. 2.1 44 memory map motorola $0014 tim channel 1 register high (tch1h) read: bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 write: reset: indeterminate after reset $0015 tim channel 1 register low (tch1l) read: bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 write: reset: indeterminate after reset $0016 keyboard status and control register (kbscr) read: 0000 keyf 0 imaskk modek write: ackk reset:00000000 $0017 keyboard interrupt enable register (kbier) read: kbie7 kbie6 kbie5 kbie4 kbie3 kbie2 kbie1 kbie0 write: reset:00000000 $0018 usb interrupt register 2 (uir2) read: 00000000 write: eopfr rstfr txd2fr rxd2fr tdx1fr resumfr txd0fr rxd0fr reset:00000000 $0019 usb control register 2 (ucr2) read: t2seq stall2 tx2e rx2e tp2siz3 tp2siz2 tp2siz1 tp2siz0 write: reset:00000000 $001a usb control register 3 (ucr3) read: tx1st 0 ostall0 istall0 0 pullen enable2 enable1 write: tx1str reset:000000*00 * pullen bit is reset by por or lvi reset only. $001b usb control register 4 (ucr4) read: 00000 fusbo fdp fdm write: reset:00000000 $001c irq option control register (iocr) read: 00000pte4if pte4ie irqpd write: reset:00000000 $001d port option control register (pocr) read: pte20p ptdldd ptdildd pte4p pte3p pcp pbp pap write: reset:00000000 addr.register name bit 7654321bit 0 = unimplemented r = reserved u = unaffected by reset figure 2-2. control, status, a nd data register s (sheet 3 of 8) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . memory map monitor rom mc68hc908jb8mc68hc08jb8mc68HC08JT8 ? rev. 2.1 technical data motorola memory map 45 $001e irq status and control register (iscr) read: 0000irqf0 imask mode write: ack reset:00000000 $001f configuration register (config) ? read: 0 0 urstd lvid ssrec coprs stop copd write: reset:00000000 ? one-time writable register after each reset. urstd and lvid bits are reset by por or lvi reset only. $0020 usb endpoint 0 data register 0 (ue0d0) read: ue0r07 ue0r06 ue0r05 ue0r04 ue0r03 ue0r02 ue0r01 ue0r00 write: ue0t07 ue0t06 ue0t05 ue0t 04 ue0t03 ue0t02 ue0t01 ue0t00 reset: unaffected by reset $0021 usb endpoint 0 data register 1 (ue0d1) read: ue0r17 ue0r16 ue0r15 ue0r14 ue0r13 ue0r12 ue0r11 ue0r10 write: ue0t17 ue0t16 ue0t15 ue0t 14 ue0t13 ue0t12 ue0t11 ue0t10 reset: unaffected by reset $0022 usb endpoint 0 data register 2 (ue0d2) read: ue0r27 ue0r26 ue0r25 ue0r24 ue0r23 ue0r22 ue0r21 ue0r20 write: ue0t27 ue0t26 ue0t25 ue0t 24 ue0t23 ue0t22 ue0t21 ue0t20 reset: unaffected by reset $0023 usb endpoint 0 data register 3 (ue0d3) read: ue0r37 ue0r36 ue0r35 ue0r34 ue0r33 ue0r32 ue0r31 ue0r30 write: ue0t37 ue0t36 ue0t35 ue0t 34 ue0t33 ue0t32 ue0t31 ue0t30 reset: unaffected by reset $0024 usb endpoint 0 data register 4 (ue0d4) read: ue0r47 ue0r46 ue0r45 ue0r44 ue0r43 ue0r42 ue0r41 ue0r40 write: ue0t47 ue0t46 ue0t45 ue0t 44 ue0t43 ue0t42 ue0t41 ue0t40 reset: unaffected by reset $0025 usb endpoint 0 data register 5 (ue0d5) read: ue0r57 ue0r56 ue0r55 ue0r54 ue0r53 ue0r52 ue0r51 ue0r50 write: ue0t57 ue0t56 ue0t55 ue0t 54 ue0t53 ue0t52 ue0t51 ue0t50 reset: unaffected by reset $0026 usb endpoint 0 data register 6 (ue0d6) read: ue0r67 ue0r66 ue0r65 ue0r64 ue0r63 ue0r62 ue0r61 ue0r60 write: ue0t67 ue0t66 ue0t65 ue0t 64 ue0t63 ue0t62 ue0t61 ue0t60 reset: unaffected by reset $0027 usb endpoint 0 data register 7 (ue0d7) read: ue0r77 ue0r76 ue0r75 ue0r74 ue0r73 ue0r72 ue0r71 ue0r70 write: ue0t77 ue0t76 ue0t75 ue0t 74 ue0t73 ue0t72 ue0t71 ue0t70 reset: unaffected by reset addr.register name bit 7654321bit 0 = unimplemented r = reserved u = unaffected by reset figure 2-2. control, status, a nd data register s (sheet 4 of 8) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . memory map technical data mc68hc908jb8mc68h c08jb8mc68HC08JT8 ? rev. 2.1 46 memory map motorola $0028 usb endpoint 1 data register 0 (ue1d0) read: write: ue1t07 ue1t06 ue1t05 ue1t 04 ue1t03 ue1t02 ue1t01 ue1t00 reset: unaffected by reset $0029 usb endpoint 1 data register 1 (ue1d1) read: write: ue1t17 ue1t16 ue1t15 ue1t 14 ue1t13 ue1t12 ue1t11 ue1t10 reset: unaffected by reset $002a usb endpoint 1 data register 2 (ue1d2) read: write: ue1t27 ue1t26 ue1t25 ue1t 24 ue1t23 ue1t22 ue1t21 ue1t20 reset: unaffected by reset $002b usb endpoint 1 data register 3 (ue1d3) read: write: ue1t37 ue1t36 ue1t35 ue1t 34 ue1t33 ue1t32 ue1t31 ue1t30 reset: unaffected by reset $002c usb endpoint 1 data register 4 (ue1d4) read: write: ue1t47 ue1t46 ue1t45 ue1t 44 ue1t43 ue1t42 ue1t41 ue1t40 reset: unaffected by reset $002d usb endpoint 1 data register 5 (ue1d5) read: write: ue1t57 ue1t56 ue1t55 ue1t 54 ue1t53 ue1t52 ue1t51 ue1t50 reset: unaffected by reset $002e usb endpoint 1 data register 6 (ue1d6) read: write: ue1t67 ue1t66 ue1t65 ue1t 64 ue1t63 ue1t62 ue1t61 ue1t60 reset: unaffected by reset $002f usb endpoint 1 data register 7 (ue1d7) read: write: ue1t77 ue1t76 ue1t75 ue1t 74 ue1t73 ue1t72 ue1t71 ue1t70 reset: unaffected by reset $0030 usb endpoint 2 data register 0 (ue2d0) read: ue2r07 ue2r06 ue2r05 ue2r04 ue2r03 ue2r02 ue2r01 ue2r00 write: ue2t07 ue2t06 ue2t05 ue2t 04 ue2t03 ue2t02 ue2t01 ue2t00 reset: unaffected by reset $0031 usb endpoint 2 data register 1 (ue2d1) read: ue2r17 ue2r16 ue2r15 ue2r14 ue2r13 ue2r12 ue2r11 ue2r10 write: ue2t17 ue2t16 ue2t15 ue2t 14 ue2t13 ue2t12 ue2t11 ue2t10 reset: unaffected by reset addr.register name bit 7654321bit 0 = unimplemented r = reserved u = unaffected by reset figure 2-2. control, status, a nd data register s (sheet 5 of 8) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . memory map monitor rom mc68hc908jb8mc68hc08jb8mc68HC08JT8 ? rev. 2.1 technical data motorola memory map 47 $0032 usb endpoint 2 data register 2 (ue2d2) read: ue2r27 ue2r26 ue2r25 ue2r24 ue2r23 ue2r22 ue2r21 ue2r20 write: ue2t27 ue2t26 ue2t25 ue2t 24 ue2t23 ue2t22 ue2t21 ue2t20 reset: unaffected by reset $0033 usb endpoint 2 data register 3 (ue2d3) read: ue2r37 ue2r36 ue2r35 ue2r34 ue2r33 ue2r32 ue2r31 ue2r30 write: ue2t37 ue2t36 ue2t35 ue2t 34 ue2t33 ue2t32 ue2t31 ue2t30 reset: unaffected by reset $0034 usb endpoint 2 data register 4 (ue2d4) read: ue2r47 ue2r46 ue2r45 ue2r44 ue2r43 ue2r42 ue2r41 ue2r40 write: ue2t47 ue2t46 ue2t45 ue2t 44 ue2t43 ue2t42 ue2t41 ue2t40 reset: unaffected by reset $0035 usb endpoint 2 data register 5 (ue2d5) read: ue2r57 ue2r56 ue2r55 ue2r54 ue2r53 ue2r52 ue2r51 ue2r50 write: ue2t57 ue2t56 ue2t55 ue2t 54 ue2t53 ue2t52 ue2t51 ue2t50 reset: unaffected by reset $0036 usb endpoint 2 data register 6 (ue2d6) read: ue2r67 ue2r66 ue2r65 ue2r64 ue2r63 ue2r62 ue2r61 ue2r60 write: ue2t67 ue2t66 ue2t65 ue2t 64 ue2t63 ue2t62 ue2t61 ue2t60 reset: unaffected by reset $0037 usb endpoint 2 data register 7 (ue2d7) read: ue2r77 ue2r76 ue2r75 ue2r74 ue2r73 ue2r72 ue2r71 ue2r70 write: ue2t77 ue2t76 ue2t75 ue2t 74 ue2t73 ue2t72 ue2t71 ue2t70 reset: unaffected by reset $0038 usb address register (uaddr) read: usben uadd6 uadd5 uadd4 uadd3 uadd2 uadd1 uadd0 write: reset:0*0000000 * usben bit is reset by por or lvi reset only. $0039 usb interrupt register 0 (uir0) read: eopie suspnd txd2ie rxd2ie txd1ie 0 txd0ie rxd0ie write: reset:00000000 $003a usb interrupt register 1 (uir1) read: eopf rstf txd2f rxd2f txd1f resumf txd0f rxd0f write: reset:00000000 $003b usb control register 0 (ucr0) read: t0seq 0 tx0e rx0e tp0siz3 tp0siz2 tp0siz1 tp0siz0 write: reset:00000000 addr.register name bit 7654321bit 0 = unimplemented r = reserved u = unaffected by reset figure 2-2. control, status, a nd data register s (sheet 6 of 8) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . memory map technical data mc68hc908jb8mc68h c08jb8mc68HC08JT8 ? rev. 2.1 48 memory map motorola $003c usb control register 1 (ucr1) read: t1seq stall1 tx1e fresum tp1siz3 tp1siz2 tp1siz1 tp1siz0 write: reset:00000000 $003d usb status register 0 (usr0) read: r0seq setup 0 0 rp0siz3 rp0siz2 rp0siz1 rp0siz0 write: reset: unaffected by reset $003e usb status register 1 (usr1) read: r2seq txack txnak txstl rp2siz3 rp2siz2 rp2siz1 rp2siz0 write: reset:u0 0 0uuuu $003f unimplemented read: write: $fe00 break status register (bsr) read: rrrrrr sbsw r write: see note reset: 0 note: writing a l ogic 0 clears sbsw. $fe01 reset status register (rsr) read: por pin cop ilop ilad usb lvi 0 write: por:10000000 $fe02 reserved read: rrrrrrrr write: $fe03 break flag control register (bfcr) read: bcferrrrrrr write: reset: 0 $fe04 interrupt status register 1 (int1) read: if6 if5 if4 if3 if2 if1 0 0 write:rrrrrrrr reset:00000000 $fe05 reserved read: rrrrrrrr write: addr.register name bit 7654321bit 0 = unimplemented r = reserved u = unaffected by reset figure 2-2. control, status, a nd data register s (sheet 7 of 8) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . memory map monitor rom mc68hc908jb8mc68hc08jb8mc68HC08JT8 ? rev. 2.1 technical data motorola memory map 49 $fe06 reserved read: rrrrrrrr write: $fe07 reserved read: rrrrrrrr write: $fe08 flash control register (flcr) read: 0000 hven mass erase pgm write: reset:00000000 $fe09 flash block protect register (flbpr) read: bpr7 bpr6 bpr5 bpr4 bpr3 bpr2 bpr1 bpr0 write: reset:00000000 $fe0a reserved read: rrrrrrrr write: $fe0b reserved read: rrrrrrrr write: $fe0c break address high register (brkh) read: bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 write: reset:00000000 $fe0d break address low register (brkl) read: bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 write: reset:00000000 $fe0e break status and control register (brkscr) read: brke brka 000000 write: reset:00000000 $ffff cop control register (copctl) read: low byte of reset vector write: writing clears co p counter (any value) reset: unaffected by reset addr.register name bit 7654321bit 0 = unimplemented r = reserved u = unaffected by reset figure 2-2. control, status, a nd data register s (sheet 8 of 8) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . memory map technical data mc68hc908jb8mc68h c08jb8mc68HC08JT8 ? rev. 2.1 50 memory map motorola table 2-1 is a list of vector locations. table 2-1. vector addresses vector priority int flag address vector lowest if6 $fff0 keyboard vector (high) $fff1 keyboard vector (low) if5 $fff2 tim overflow vector (high) $fff3 tim overflow vector (low) if4 $fff4 tim channel 1 vector (high) $fff5 tim channel 1 vector (low) if3 $fff6 tim channel 0 vector (high) $fff7 tim channel 0 vector (low) if1 $fff8 irq vector (high) $fff9 irq vector (low) if2 $fffa usb vector (high) $fffb usb vector (low) ? $fffc swi vector (high) $fffd swi vector (low) ? $fffe reset vector (high) highest $ffff reset vector (low) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc908jb8mc68hc08jb8mc68HC08JT8 ? rev. 2.1 technical data motorola random-access memory (ram) 51 technical data ? mc68hc908jb8?mc68hc08jb8?mc68HC08JT8 section 3. random-access memory (ram) 3.1 contents 3.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 3.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 3.2 introduction this section describes the 256 bytes of ram. 3.3 functional description addresses $0040?$013f are ram locati ons. the location of the stack ram is programmable. the 16-bit stack pointer a llows the stack to be anywhere in the 64-kb yte memory space. note: for correct operation, the stack pointer must point only to ram locations. within page zero are 192 bytes of ra m. because the location of the stack ram is programmable, all page zero ram locations can be used for i/o control and user data or code. when the stack pointer is moved from its reset location at $00ff, dire ct addressing mode instructions can access efficiently all page zero ram locations. pa ge zero ram, therefore, provides ideal locati ons for frequently accessed global variables. before processing an interrupt, the cp u uses five bytes of the stack to save the contents of the cpu registers. note: for m6805 family compatib ility, the h regist er is not stacked. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . random-access memory (ram) technical data mc68hc908jb8mc68h c08jb8mc68HC08JT8 ? rev. 2.1 52 random-access memory (ram) motorola during a subroutine call, the cpu uses two bytes of the stack to store the return address. the stack po inter decrements during pushes and increments during pulls. note: be careful when using nested subr outines. the cpu ma y overwrite data in the ram during a s ubroutine or during the interrupt stacking operation. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc908jb8mc68hc08jb8mc68HC08JT8 ? rev. 2.1 technical data motorola flash memory 53 technical data ? mc68hc908jb8?mc68hc08jb8?mc68HC08JT8 section 4. flash memory 4.1 contents 4.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 4.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 4.4 flash control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 4.5 flash block erase operatio n . . . . . . . . . . . . . . . . . . . . . . . . . 56 4.6 flash mass erase operation . . . . . . . . . . . . . . . . . . . . . . . . . 57 4.7 flash program operation. . . . . . . . . . . . . . . . . . . . . . . . . . . .58 4.8 flash protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 4.8.1 flash block protect regi ster . . . . . . . . . . . . . . . . . . . . . . . 60 4.9 rom-resident routines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 4.9.1 variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 4.9.2 erase routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 4.9.3 program routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 4.9.4 verify routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 4.2 introduction this section describes the operat ion of the embedd ed flash memory. this memory can be r ead, programmed, and er ased from a single external supply. the program and er ase operations are enabled through the use of an internal charge pump. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . flash memory technical data mc68hc908jb8mc68h c08jb8mc68HC08JT8 ? rev. 2.1 54 flash memory motorola 4.3 functional description the flash memory consists of an arra y of 8,192 bytes for user memory plus a small block of 16 bytes for user interrupt vectors. an erased bit reads as logic 1 an d a programmed bit r eads as a logic 0. the flash memory is block erasable. the minimu m erase block size is 512 bytes. program and erase operat ion operations are facilitated through control bits in flash control register (flcr).the address ranges for the flash memory are shown as follows: $dc00?$fbff (user memory; 8,192 bytes) $fff0?$ffff (user interrupt vectors; 16 bytes) programming tools are available from motorola. contact your local motorola representative for more information. note: a security feature prevents vi ewing of the flash contents. 1 addr. register name bit 7 6 5 4 3 2 1 bit 0 $fe08 flash control register (flcr) read: 0000 hven mass erase pgm write: reset:00000000 $fe09 flash block protect register (flbpr) read: bpr7 bpr6 bpr5 bpr4 bpr3 bpr2 bpr1 bpr0 write: reset:00000000 figure 4-1. fla sh memory register summary 1. no security feature is absolutely secure. howe ver, motorola?s strategy is to make reading or copying the flash difficult for unauthorized users. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . flash memory flash control register mc68hc908jb8mc68hc08jb8mc68HC08JT8 ? rev. 2.1 technical data motorola flash memory 55 4.4 flash control register the flash control register (flcr) controls flash program and erase operations. hven ? high voltage enable bit this read/write bit enables high vo ltage from the charge pump to the memory for either progra m or erase operation. it can only be set if either pgm or erase is high and the s equence for erase or program/verify is followed. 1 = high voltage enabled to array and charge pump on 0 = high voltage disabled to array and charge pump off mass ? mass erase control bit this read/write bit confi gures the memory for mass erase operation or block erase operation when the erase bit is set. 1 = mass erase operation selected 0 = block erase operation selected erase ? erase control bit this read/write bit confi gures the memory for erase operation. this bit and the pgm bit should not be se t to 1 at t he same time. 1 = erase operation selected 0 = erase operation not selected pgm ? program control bit this read/write bit confi gures the memory for program operation. this bit and the erase bit s hould not be set to 1 at the same time. 1 = program operation selected 0 = program operation not selected address: $fe08 bit 7654321bit 0 read: 0000 hven mass erase pgm write: reset:00000000 figure 4-2. flash cont rol register (flcr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . flash memory technical data mc68hc908jb8mc68h c08jb8mc68HC08JT8 ? rev. 2.1 56 flash memory motorola 4.5 flash block erase operation use the following procedure to erase a block of flash memory. a block consists of 512 consecutive byte s starting from addresses $x000, $x200, $x400, $x600, $x800, $x a00, $xc00 or $xe00. any block within the 8,192 bytes user me mory area ($ dc00?$fbff) can be erased alone. note: the 16-byte user vector s, $fff0?$ffff, cannot be er ased by the block erase operation because of security reasons. mass erase is required to erase this block. 1. set the erase bit and clear the mass bit in th e flash control register. 2. write any data to any flash addr ess within the address range of the block to be erased. 3. wait for a time, t nvs (5 s). 4. set the hven bit. 5. wait for a time t erase (2 ms). 6. clear the erase bit. 7. wait for a time, t nvh (5 s). 8. clear the hven bit. 9. after time, t rcv (1 s), the memory can be accessed in read mode again. note: programming and erasing of flash locations c annot be performed by code being executed from the flash memory. while these operations must be performed in the order as shown, but ot her unrelated operations may occur between the steps. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . flash memory flash mass erase operation mc68hc908jb8mc68hc08jb8mc68HC08JT8 ? rev. 2.1 technical data motorola flash memory 57 4.6 flash mass erase operation use the following proc edure to erase the en tire flash memory: 1. set both the erase bit and the mass bit in the flash control register. 2. write any data to any flash address within the address range $ffe0?$ffff. 3. wait for a time, t nvs (5 s). 4. set the hven bit. 5. wait for a time t me (2 ms). 6. clear the erase bit. 7. wait for a time, t nvh1 (100 s). 8. clear the hven bit. 9. after time, t rcv (1 s), the memory can be accessed in read mode again. note: programming and erasing of flash locations c annot be performed by code being executed from the flash memory. while these operations must be performed in the order as shown, but ot her unrelated operations may occur between the steps. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . flash memory technical data mc68hc908jb8mc68h c08jb8mc68HC08JT8 ? rev. 2.1 58 flash memory motorola 4.7 flash program operation programming of the flash memory is done on a row basis. a row consists of 64 consecutive bytes starting from a ddresses $xx00, $xx40, $xx80 or $xxc0. the procedure for progr amming a row of the flash memory is outlined below: 1. set the pgm bit. this configur es the memory for program operation and enables the latchi ng of address and data for programming. 2. write any data to any flash addr ess within the address range of the row to be programmed. 3. wait for a time, t nvs (5 s). 4. set the hven bit. 5. wait for a time, t pgs (10 s). 6. write data to the by te being programmed. 7. wait for time, t prog (20 s). 8. repeat step 6 and 7 until all the bytes within the row are programmed. 9. clear the pgm bit. 10. wait for time, t nvh (5 s). 11. clear the hven bit. 12. after time, t rcv (1 s), the memory can be accessed in read mode again. this program sequence is repeated th roughout the memory until all data is programmed. note: programming and erasing of flash locations c annot be performed by code being executed from the flash memory. while these operations must be performed in the order shown, other unrelated operations may occur between the steps. do not exceed t prog maximum (see 18.13 memory characteristics ). figure 4-3 shows a flowchart represen tation for programming the flash memory. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . flash memory flash program operation mc68hc908jb8mc68hc08jb8mc68HC08JT8 ? rev. 2.1 technical data motorola flash memory 59 figure 4-3. flash programming flowchart set hven bit write any data to any flash address within the row address range desired wait for a time, t nvs set pgm bit wait for a time, t pgs write data to the flash address to be programmed wait for a time, t prog clear pgm bit wait for a time, t nvh clear hven bit wait for a time, t rcv completed programming this row? y n end of programming the time between each flash address change (step 6 to step 6), or must not exceed the maximum programming time, t prog max. the time between the last flash address programmed to clearing pgm bit (step 6 to step 9) note: 1 2 3 4 5 6 7 9 10 11 12 algorithm for programming a row (64 bytes) of flash memory this row program algorithm assumes the row/s to be programmed are initially erased. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . flash memory technical data mc68hc908jb8mc68h c08jb8mc68HC08JT8 ? rev. 2.1 60 flash memory motorola 4.8 flash protection due to the ability of the on-board charge pump to erase and program the flash memory in the tar get application, provis ion is made to protect blocks of memory from unintentional erase or program operations due to system malfunction. this protection is done by use of a flash block protect register (flb pr). the flbpr determine s the range of the flash memory which is to be prot ected. the range of the protected area starts from a location defined by flbpr and ends to the bottom of the flash memory ($ffff). when the memory is protected, the hven bit cannot be set in either erase or prog ram operations. note: when the flbpr is cleared (all 0?s) , the entire flash memory is protected from being prog rammed and erased. when all the bits are set, the entire flash memory is a ccessible for program and erase. 4.8.1 flash block protect register the flash block protect regi ster is implemented as an 8-bit i/o register. the content of this regi ster determine the sta rting location of the protected range within the flash memory. bpr[7:0] ? flash blo ck protect register bit 7 to bit 0 bpr[7:1] represent bits [15:9] of a 16-bit memory address; bits [8:0] are logic 0?s. figure 4-5. flash block protect start address address: $fe09 bit 7654321bit 0 read: bpr7 bpr6 bpr5 bpr4 bpr3 bpr2 bpr1 bpr0 write: reset:00000000 figure 4-4. flash block pr otect register (flbpr) 16-bit memory address start address of flash block protect 000000000 bpr[7:1] f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . flash memory rom-resident routines mc68hc908jb8mc68hc08jb8mc68HC08JT8 ? rev. 2.1 technical data motorola flash memory 61 bpr0 is used only for bpr[7:0] = $ff, for no block protection. the resultant 16-bit address is used for specifying the start address of the flash memory for block pr otection. the flash is protected from this start address to the end of flash me mory, at $ffff. with this mechanism, the pr otect start address can be x000, x200, x400, x600, x800, xa00, xc00, or xe00 within the flash memory. examples of protect start address: 4.9 rom-resident routines rom-resident routin es can be called by a progr am running in user mode or in monitor mode (see section 10. monitor rom (mon) ) for flash programming, erasing, and verifying. the range of t he flash memory must be unprot ected (see 4.8 flash protection ) before calling the erase or programming routine. bpr[7:0] start of address of protect range $00 to $dc the entire flash memory is protected. $de ( 1101 1110 ) $de00 ( 1101 1110 0000 0000) $e0 ( 1110 0000 )$e000 ( 1110 0000 0000 0000) $e2 ( 1110 0010 )$e200 ( 1110 0010 0000 0000) $e4 ( 1110 0100 )$e400 ( 1110 0100 0000 0000) and so on... $fe $ffe0?$ffff (user vectors) $ff the entire flash memory is not protected. note: the end address of the protected range is always $ffff. table 4-1. rom-resident routines routine name call address routine function verify $fc03 flash verify routine erase $fc06 flash mass erase routine program $fc09 flash program routine f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . flash memory technical data mc68hc908jb8mc68h c08jb8mc68HC08JT8 ? rev. 2.1 62 flash memory motorola 4.9.1 variables the rom-resident r outines use three vari ables: ctrlbyt, cpuspd and laddr; and one data buffer. the minimum si ze of the data buffer is one byte and the maxi mum size is 64 bytes. cpuspd must be set before calli ng the erase or pr ogram routine, and should be set to four times the va lue of the cpu in ternal bus speed in mhz. for example: for cpu speed of 3m hz, cpuspd should be set to 12. 4.9.2 erase routine the erase routine erases the enti re flash memory. the routine does not check for a blank ra nge before or after erase. table 4-2. rom-reside nt routine variables variable address description ctrlbyt $0048 control byte for setting mass erase. cpuspd $0049 timing adjustment for different cpu speeds. laddr $004a?$004b last flash address to be programmed. databuf $004c?$008b data buffer for programming and verifying. table 4-3. erase routine routine erase calling address $fc06 stack use 5 bytes input cpuspd ? cpu speed hx ? contains any address in the range to be erased ctrlbyt ? mass erase mass erase if bit 6 = 1 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . flash memory rom-resident routines mc68hc908jb8mc68hc08jb8mc68HC08JT8 ? rev. 2.1 technical data motorola flash memory 63 4.9.3 program routine the program routine pr ograms a range of addresses in flash memory, which does no t have to be on page boundaries, either at the begin or end address. 4.9.4 verify routine the verify routine reads and veri fies a range of flash memory. table 4-4. program routine routine program calling address $fc09 stack use 7 bytes input cpuspd ? cpu speed hx ? flash start address to be programmed laddr ? flash end address to be programmed databuf ? contains the data to be programmed table 4-5. verify routine routine verify calling address $fc03 stack use 6 bytes input hx ? flash start address to be verified laddr ? flash end address to be verified databuf ? contains the data to be verified output c bit ? c bit is set if verify passes databuf ? contains the data in the range of the flash memory f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . flash memory technical data mc68hc908jb8mc68h c08jb8mc68HC08JT8 ? rev. 2.1 64 flash memory motorola f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc908jb8mc68hc08jb8mc68HC08JT8 ? rev. 2.1 technical data motorola configuration register (config) 65 technical data ? mc68hc908jb8?mc68hc08jb8?mc68HC08JT8 section 5. configuration register (config) 5.1 contents 5.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 5.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 5.2 introduction this section describes th e configuration register (config). this write- once-after-reset register cont rols the following options: usb reset low voltage inhibit stop mode recovery time (2048 or 4096 oscxclk cycles) cop timeout period (2 18 ? 2 4 or 2 13 ? 2 4 oscxclk cycles) stop instruction computer operating pr operly module (cop) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . configuration register (config) technical data mc68hc908jb8mc68h c08jb8mc68HC08JT8 ? rev. 2.1 66 configuration register (config) motorola 5.3 functional description the configuration register is used in the initialization of various options. the configuration register can be written once af ter each reset. bit-5 and bit-4 are cleared by a por or lvi reset only. bit- 3 to bit-0 are cleared during any reset. since the various options affe ct the operation of the mcu, it is recommended that this r egister be written immediately after reset. the configuration register is located at $001f. the co nfiguration register may be r ead at any time. urstd ? usb reset disable bit urstd disables the usb reset signal generating an internal reset to the cpu and internal regi sters. instead, it wil l generate an interrupt request to the cpu. 1 = usb reset generates a usb interrupt request to cpu 0 = usb reset generat es a chip reset lvid ? low voltage in hibit disable bit lvid disables the lvi circuit 1 = disable lvi circuit 0 = enable lvi circuit ssrec ? short stop recovery bit ssrec enables the cpu to ex it stop mode with a delay of 2048 oscxclk cycles instead of a 4096 oscxclk cycle delay. 1 = stop mode re covery after 2048 oscxclk cycles 0 = stop mode re covery after 4096 oscxclk cycles address: $001f bit 7654321bit 0 read: 0 0 urstd lvid ssrec coprs stop copd write: reset:000*0*0000 = unimplemented * urstd and lvid bits are reset by por or lvi reset only. figure 5-1. configurat ion register (config) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . configuration register (config) functional description mc68hc908jb8mc68hc08jb8mc68HC08JT8 ? rev. 2.1 technical data motorola configuration register (config) 67 note: exiting stop mode by pulling reset will result in the long stop recovery. if using an external crystal , do not set t he ssrec bit. coprs ? cop rate select bit copd selects the cop timeout per iod. reset clears coprs. (see section 15. computer o perating properly (cop) .) 1 = cop timeout period = (2 13 ? 2 4 ) oscxclk cycles 0 = cop timeout period = (2 18 ? 2 4 ) oscxclk cycles stop ? stop instruction enable bit stop enables the stop instruction. 1 = stop inst ruction enabled 0 = stop instruction tr eated as illegal opcode copd ? cop disable bit copd disables the cop module. (see section 15. computer operating properly (cop) .) 1 = cop module disabled 0 = cop module enabled f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . configuration register (config) technical data mc68hc908jb8mc68h c08jb8mc68HC08JT8 ? rev. 2.1 68 configuration register (config) motorola f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc908jb8mc68hc08jb8mc68HC08JT8 ? rev. 2.1 technical data motorola central processor unit (cpu) 69 technical data ? mc68hc908jb8?mc68hc08jb8?mc68HC08JT8 section 6. central processor unit (cpu) 6.1 contents 6.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 6.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 6.4 cpu registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 6.4.1 accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 6.4.2 index register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 6.4.3 stack pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 6.4.4 program counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 6.4.5 condition code register . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 6.5 arithmetic/logic unit (alu) . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 6.6 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 6.6.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76 6.6.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77 6.7 cpu during break interrupt s . . . . . . . . . . . . . . . . . . . . . . . . . . 77 6.8 instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 6.9 opcode map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processor unit (cpu) technical data mc68hc908jb8mc68h c08jb8mc68HC08JT8 ? rev. 2.1 70 central processor unit (cpu) motorola 6.2 introduction the m68hc08 cpu (central proce ssor unit) is an enhanced and fully object-code-compatible vers ion of the m 68hc05 cpu. the cpu08 reference manual (motorola document or der number cpu08rm/ad) contains a description of the cpu instruction set, addressing modes, and architecture. 6.3 features object code fully upward-com patible with m68hc05 family 16-bit stack pointer with st ack manipulation instructions 16-bit index register with x-regi ster manipulation instructions 3-mhz cpu internal bus frequency 64-kbyte program/data memory space 16 addressing modes memory-to-memory data moves without using accumulator fast 8-bit by 8-bit multiply and 16-bit by 8-bit divide instructions enhanced binary-coded decim al (bcd) data handling modular architecture with exp andable internal bu s definition for extension of addressi ng range beyond 64-kbytes low-power stop and wait modes f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processor unit (cpu) cpu registers mc68hc908jb8mc68hc08jb8mc68HC08JT8 ? rev. 2.1 technical data motorola central processor unit (cpu) 71 6.4 cpu registers figure 6-1 shows the five cpu registers. cpu regist ers are not part of the memory map. figure 6-1. cpu registers 6.4.1 accumulator the accumulator is a general-purpose 8- bit register. the cpu uses the accumulator to hold operands and th e results of arithmetic/logic operations. accumulator (a) index register (h:x) stack pointer (sp) program counter (pc) condition code register (ccr) carry/borrow flag zero flag negative flag interrupt mask half-carry flag two?s complement overflow flag v11hinzc h x 0 0 0 0 7 15 15 15 70 bit 7654321bit 0 read: write: reset: unaffected by reset figure 6-2. accumulator (a) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processor unit (cpu) technical data mc68hc908jb8mc68h c08jb8mc68HC08JT8 ? rev. 2.1 72 central processor unit (cpu) motorola 6.4.2 index register the 16-bit index register allows indexed addressing of a 64-kbyte memory space. h is the upper byte of the index regi ster, and x is the lower byte. h:x is the conc atenated 16-bit index register. in the indexed addressi ng modes, the cpu uses the contents of the index register to determine the conditional addr ess of the operand. the index register can serve also as a temporary data storage location. 6.4.3 stack pointer the stack pointer is a 16-bi t register that contains the address of the next location on the stack. during a rese t, the stack pointer is preset to $00ff. the reset stack pointer (rsp ) instruction sets the least significant byte to $ff and does not af fect the most significant byte. the stack pointer decrements as data is pushed onto the stack and increments as data is pulled from the stack. in the stack pointer 8-bi t offset and 16-bit offs et addressing modes, the stack pointer can functi on as an index register to access data on the stack. the cpu uses the contents of the stack pointer to determine the conditional address of the operand. bit 15 1413121110987654321 bit 0 read: write: reset:00000000 xxxxxxxx x = indeterminate figure 6-3. index register (h:x) bit 15 1413121110987654321 bit 0 read: write: reset:0000000011111111 figure 6-4. stack pointer (sp) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processor unit (cpu) cpu registers mc68hc908jb8mc68hc08jb8mc68HC08JT8 ? rev. 2.1 technical data motorola central processor unit (cpu) 73 note: the location of the stack is arbitr ary and may be relocated anywhere in ram. moving the sp out of page 0 ($0000 to $00ff) frees direct address (page 0) space. for correct operation, t he stack pointer must point only to ram locations. 6.4.4 program counter the program counter is a 16-bit register that contains the address of the next instruction or operand to be fetched. normally, the program counter autom atically increm ents to the next sequential memory location every time an instruct ion or operand is fetched. jump, branch, and interr upt operations l oad the program counter with an addr ess other than that of the next sequential location. during reset, the program counter is loaded with the reset vector address located at $fffe and $ffff. the vect or address is the address of the first instruction to be executed after exiti ng the reset state. bit 15 1413121110987654321 bit 0 read: write: reset: loaded with vector from $fffe and $ffff figure 6-5. prog ram counter (pc) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processor unit (cpu) technical data mc68hc908jb8mc68h c08jb8mc68HC08JT8 ? rev. 2.1 74 central processor unit (cpu) motorola 6.4.5 condition code register the 8-bit condition code register cont ains the interrupt mask and five flags that indicate the re sults of the instruction just executed. bits 6 and 5 are set permanently to logic 1. the following paragraphs describe the functions of the cond ition code register. v ? overflow flag the cpu sets the overfl ow flag when a two's complement overflow occurs. the signed branch instructi ons bgt, bge, ble, and blt use the overflow flag. 1 = overflow 0 = no overflow h ? half-carry flag the cpu sets the half-carry fl ag when a carry occurs between accumulator bits 3 and 4 during an add-without-car ry (add) or add- with-carry (adc) operat ion. the half-carry flag is required for binary- coded decimal (bcd) arithmetic oper ations. the daa instruction uses the states of the h and c flags to determine t he appropriate correction factor. 1 = carry between bits 3 and 4 0 = no carry between bits 3 and 4 bit 7654321bit 0 read: v11hinzc write: reset:x11x1xxx x = indeterminate figure 6-6. condition code register (ccr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processor unit (cpu) cpu registers mc68hc908jb8mc68hc08jb8mc68HC08JT8 ? rev. 2.1 technical data motorola central processor unit (cpu) 75 i ? interrupt mask when the interrupt mask is set, all maskable cpu interrupts are disabled. cpu interrupts are ena bled when the interrupt mask is cleared. when a cpu in terrupt occurs, the interrupt mask is set automatically after t he cpu registers are sa ved on the stack, but before the interrupt vector is fetched. 1 = interrupts disabled 0 = interrupts enabled note: to maintain m6805 family compatibility, the upper byte of the index register (h) is not sta cked automatically. if the interrupt service routine modifies h, then the user must stack and unstack h using the pshh and pulh instructions. after the i bit is clear ed, the highest-priority interrupt request is serviced first. a return-from-interrupt (rti) instru ction pulls the cp u registers from the stack and restores the interr upt mask from the stack. after any reset, the interrupt mask is set and can be cleared only by the clear interrupt mask software instruction (cli). n ? negative flag the cpu sets the negative flag when an arithmet ic operation, logic operation, or data manipulation pr oduces a negative result, setting bit 7 of the result. 1 = negative result 0 = non-negative result z ? zero flag the cpu sets the zero flag when an arithmetic operation, logic operation, or data manipulati on produces a result of $00. 1 = zero result 0 = non-zero result f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processor unit (cpu) technical data mc68hc908jb8mc68h c08jb8mc68HC08JT8 ? rev. 2.1 76 central processor unit (cpu) motorola c ? carry/borrow flag the cpu sets the carry/borrow flag when an addition operation produces a carry out of bit 7 of the accumulator or when a subtraction operation requires a borrow. some instructions ? such as bit test and branch, shift, and rotate ? also clear or set the carry/borrow flag. 1 = carry out of bit 7 0 = no carry out of bit 7 6.5 arithmetic/l ogic unit (alu) the alu performs the arit hmetic and logic operat ions defined by the instruction set. refer to the cpu08 reference manual (motorola document order number cpu08rm/ad) for a descripti on of the instructions and addressing modes and more detail about the architectu re of the cpu. 6.6 low-power modes the wait and stop instructions put the mcu in low power-consumption standby modes. 6.6.1 wait mode the wait instruction: clears the interrupt ma sk (i bit) in the condi tion code register, enabling interrupts. after exit from wait mode by interrupt, the i bit remains clear. after exit by reset, the i bit is set. disables the cpu clock f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processor unit (cpu) cpu during break interrupts mc68hc908jb8mc68hc08jb8mc68HC08JT8 ? rev. 2.1 technical data motorola central processor unit (cpu) 77 6.6.2 stop mode the stop instruction: clears the interrupt ma sk (i bit) in the condi tion code register, enabling external interrupts. after exit from stop mode by external interrupt, the i bit remains clear. afte r exit by reset, the i bit is set. disables the cpu clock after exiting stop mode, t he cpu clock begins running after the oscillator stabilization delay. 6.7 cpu during break interrupts if a break module is present on the mcu, the cpu starts a break interrupt by: loading the instruction regist er with the swi instruction loading the program counter with $fffc:$fffd or with $fefc:$fefd in monitor mode the break interrupt begins after completion of t he cpu instruction in progress. if the break address register match occurs on the last cycle of a cpu instruction, the break interrupt begins immediately. a return-from-interrupt instruction (rti) in the break routine ends the break interrupt and retu rns the mcu to normal operation if the break interrupt has been deasserted. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processor unit (cpu) technical data mc68hc908jb8mc68h c08jb8mc68HC08JT8 ? rev. 2.1 78 central processor unit (cpu) motorola 6.8 instruction set summary table 6-1. instruction se t summary (sheet 1 of 9) source form operation description effect on ccr address mode opcode operand cycles vh i nzc adc # opr adc opr adc opr adc opr ,x adc opr ,x adc ,x adc opr ,sp adc opr ,sp add with carry a (a) + (m) + (c) tt ? ttt imm dir ext ix2 ix1 ix sp1 sp2 a9 b9 c9 d9 e9 f9 9ee9 9ed9 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 add # opr add opr add opr add opr ,x add opr ,x add ,x add opr ,sp add opr ,sp add without carry a (a) + (m) tt ? ttt imm dir ext ix2 ix1 ix sp1 sp2 ab bb cb db eb fb 9eeb 9edb ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 ais # opr add immediate value (signed) to sp sp (sp) + (16 ? m) ??????imm a7 ii 2 aix # opr add immediate value (signed) to h:x h:x (h:x) + (16 ? m) ??????imm af ii 2 and # opr and opr and opr and opr ,x and opr ,x and ,x and opr ,sp and opr ,sp logical and a (a) & (m) 0 ? ? tt ? imm dir ext ix2 ix1 ix sp1 sp2 a4 b4 c4 d4 e4 f4 9ee4 9ed4 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 asl opr asla aslx asl opr ,x asl ,x asl opr ,sp arithmetic shift left (same as lsl) t ?? ttt dir inh inh ix1 ix sp1 38 48 58 68 78 9e68 dd ff ff 4 1 1 4 3 5 asr opr asra asrx asr opr ,x asr opr ,x asr opr ,sp arithmetic shift right t ?? ttt dir inh inh ix1 ix sp1 37 47 57 67 77 9e67 dd ff ff 4 1 1 4 3 5 c b0 b7 0 b0 b7 c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processor unit (cpu) instruction set summary mc68hc908jb8mc68hc08jb8mc68HC08JT8 ? rev. 2.1 technical data motorola central processor unit (cpu) 79 bcc rel branch if carry bit clear pc (pc) + 2 + rel ? (c) = 0 ? ? ? ? ? ? rel 24 rr 3 bclr n , opr clear bit n in m mn 0 ?????? dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 11 13 15 17 19 1b 1d 1f dd dd dd dd dd dd dd dd 4 4 4 4 4 4 4 4 bcs rel branch if carry bit set (same as blo) pc (pc) + 2 + rel ? (c) = 1 ??????rel 25 rr 3 beq rel branch if equal pc (pc) + 2 + rel ? (z) = 1 ??????rel 27 rr 3 bge opr branch if greater than or equal to (signed operands) pc (pc) + 2 + rel ? (n v) = 0 ??????rel 90 rr 3 bgt opr branch if greater than (signed operands) pc (pc) + 2 + rel ? (z) | (n v) = 0 ??????rel 92 rr 3 bhcc rel branch if half carry bit clear pc (pc) + 2 + rel ? (h) = 0 ??????rel 28 rr 3 bhcs rel branch if half carry bit set pc (pc) + 2 + rel ? (h) = 1 ??????rel 29 rr 3 bhi rel branch if higher pc (pc) + 2 + rel ? (c) | (z) = 0 ? ? ? ? ? ? rel 22 rr 3 bhs rel branch if higher or same (same as bcc) pc (pc) + 2 + rel ? (c) = 0 ??????rel 24 rr 3 bih rel branch if irq pin high pc (pc) + 2 + rel ? irq = 1 ??????rel 2f rr 3 bil rel branch if irq pin low pc (pc) + 2 + rel ? irq = 0 ??????rel 2e rr 3 bit # opr bit opr bit opr bit opr ,x bit opr ,x bit ,x bit opr ,sp bit opr ,sp bit test (a) & (m) 0 ? ? tt ? imm dir ext ix2 ix1 ix sp1 sp2 a5 b5 c5 d5 e5 f5 9ee5 9ed5 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 ble opr branch if less than or equal to (signed operands) pc (pc) + 2 + rel ? (z) | (n v ) = 1 ??????rel 93 rr 3 blo rel branch if lower (same as bcs) pc (pc) + 2 + rel ? (c) = 1 ??????rel 25 rr 3 bls rel branch if lower or same pc (pc) + 2 + rel ? (c) | (z) = 1 ? ? ? ? ? ? rel 23 rr 3 blt opr branch if less than (signed operands) pc (pc) + 2 + rel ? (n v ) = 1 ??????rel 91 rr 3 bmc rel branch if interrupt mask clear pc (pc) + 2 + rel ? (i) = 0 ??????rel 2c rr 3 bmi rel branch if minus pc (pc) + 2 + rel ? (n) = 1 ??????rel 2b rr 3 bms rel branch if interrupt mask set pc (pc) + 2 + rel ? (i) = 1 ??????rel 2d rr 3 table 6-1. instruction se t summary (sheet 2 of 9) source form operation description effect on ccr address mode opcode operand cycles vh i nzc f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processor unit (cpu) technical data mc68hc908jb8mc68h c08jb8mc68HC08JT8 ? rev. 2.1 80 central processor unit (cpu) motorola bne rel branch if not equal pc (pc) + 2 + rel ? (z) = 0 ??????rel 26 rr 3 bpl rel branch if plus pc (pc) + 2 + rel ? (n) = 0 ??????rel 2a rr 3 bra rel branch always pc (pc) + 2 + rel ??????rel 20 rr 3 brclr n , opr , rel branch if bit n in m clear pc (pc) + 3 + rel ? (mn) = 0 ????? t dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 01 03 05 07 09 0b 0d 0f dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr 5 5 5 5 5 5 5 5 brn rel branch never pc (pc) + 2 ??????rel 21 rr 3 brset n , opr , rel branch if bit n in m set pc (pc) + 3 + rel ? (mn) = 1 ????? t dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 00 02 04 06 08 0a 0c 0e dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr 5 5 5 5 5 5 5 5 bset n , opr set bit n in m mn 1 ?????? dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 10 12 14 16 18 1a 1c 1e dd dd dd dd dd dd dd dd 4 4 4 4 4 4 4 4 bsr rel branch to subroutine pc (pc) + 2; push (pcl) sp (sp) ? 1; push (pch) sp (sp) ? 1 pc (pc) + rel ??????rel ad rr 4 cbeq opr,rel cbeqa # opr,rel cbeqx # opr,rel cbeq opr, x+ ,rel cbeq x+ ,rel cbeq opr, sp ,rel compare and branch if equal pc (pc) + 3 + rel ? (a) ? (m) = $00 pc (pc) + 3 + rel ? (a) ? (m) = $00 pc (pc) + 3 + rel ? (x) ? (m) = $00 pc (pc) + 3 + rel ? (a) ? (m) = $00 pc (pc) + 2 + rel ? (a) ? (m) = $00 pc (pc) + 4 + rel ? (a) ? (m) = $00 ?????? dir imm imm ix1+ ix+ sp1 31 41 51 61 71 9e61 dd rr ii rr ii rr ff rr rr ff rr 5 4 4 5 4 6 clc clear carry bit c 0 ?????0inh 98 1 cli clear interrupt mask i 0 ??0???inh 9a 2 table 6-1. instruction se t summary (sheet 3 of 9) source form operation description effect on ccr address mode opcode operand cycles vh i nzc f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processor unit (cpu) instruction set summary mc68hc908jb8mc68hc08jb8mc68HC08JT8 ? rev. 2.1 technical data motorola central processor unit (cpu) 81 clr opr clra clrx clrh clr opr ,x clr ,x clr opr ,sp clear m $00 a $00 x $00 h $00 m $00 m $00 m $00 0??01? dir inh inh inh ix1 ix sp1 3f 4f 5f 8c 6f 7f 9e6f dd ff ff 3 1 1 1 3 2 4 cmp # opr cmp opr cmp opr cmp opr ,x cmp opr ,x cmp ,x cmp opr ,sp cmp opr ,sp compare a with m (a) ? (m) t ?? ttt imm dir ext ix2 ix1 ix sp1 sp2 a1 b1 c1 d1 e1 f1 9ee1 9ed1 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 com opr coma comx com opr ,x com ,x com opr ,sp complement (one?s complement) m (m ) = $ff ? (m) a (a ) = $ff ? (m) x (x ) = $ff ? (m) m (m ) = $ff ? (m) m (m ) = $ff ? (m) m (m ) = $ff ? (m) 0?? tt 1 dir inh inh ix1 ix sp1 33 43 53 63 73 9e63 dd ff ff 4 1 1 4 3 5 cphx # opr cphx opr compare h:x with m (h:x) ? (m:m + 1) t ?? ttt imm dir 65 75 ii ii+1 dd 3 4 cpx # opr cpx opr cpx opr cpx ,x cpx opr ,x cpx opr ,x cpx opr ,sp cpx opr ,sp compare x with m (x) ? (m) t ?? ttt imm dir ext ix2 ix1 ix sp1 sp2 a3 b3 c3 d3 e3 f3 9ee3 9ed3 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 daa decimal adjust a (a) 10 u?? ttt inh 72 2 dbnz opr,rel dbnza rel dbnzx rel dbnz opr, x ,rel dbnz x ,rel dbnz opr, sp ,rel decrement and branch if not zero a (a) ? 1 or m (m) ? 1 or x (x) ? 1 pc (pc) + 3 + rel ? (result) 0 pc (pc) + 2 + rel ? (result) 0 pc (pc) + 2 + rel ? (result) 0 pc (pc) + 3 + rel ? (result) 0 pc (pc) + 2 + rel ? (result) 0 pc (pc) + 4 + rel ? (result) 0 ?????? dir inh inh ix1 ix sp1 3b 4b 5b 6b 7b 9e6b dd rr rr rr ff rr rr ff rr 5 3 3 5 4 6 dec opr deca decx dec opr ,x dec ,x dec opr ,sp decrement m (m) ? 1 a (a) ? 1 x (x) ? 1 m (m) ? 1 m (m) ? 1 m (m) ? 1 t ?? tt ? dir inh inh ix1 ix sp1 3a 4a 5a 6a 7a 9e6a dd ff ff 4 1 1 4 3 5 div divide a (h:a)/(x) h remainder ???? tt inh 52 7 table 6-1. instruction se t summary (sheet 4 of 9) source form operation description effect on ccr address mode opcode operand cycles vh i nzc f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processor unit (cpu) technical data mc68hc908jb8mc68h c08jb8mc68HC08JT8 ? rev. 2.1 82 central processor unit (cpu) motorola eor # opr eor opr eor opr eor opr ,x eor opr ,x eor ,x eor opr ,sp eor opr ,sp exclusive or m with a a (a m) 0?? tt ? imm dir ext ix2 ix1 ix sp1 sp2 a8 b8 c8 d8 e8 f8 9ee8 9ed8 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 inc opr inca incx inc opr ,x inc ,x inc opr ,sp increment m (m) + 1 a (a) + 1 x (x) + 1 m (m) + 1 m (m) + 1 m (m) + 1 t ?? tt ? dir inh inh ix1 ix sp1 3c 4c 5c 6c 7c 9e6c dd ff ff 4 1 1 4 3 5 jmp opr jmp opr jmp opr ,x jmp opr ,x jmp ,x jump pc jump address ?????? dir ext ix2 ix1 ix bc cc dc ec fc dd hh ll ee ff ff 2 3 4 3 2 jsr opr jsr opr jsr opr ,x jsr opr ,x jsr ,x jump to subroutine pc (pc) + n ( n = 1, 2, or 3) push (pcl); sp (sp) ? 1 push (pch); sp (sp) ? 1 pc unconditional address ?????? dir ext ix2 ix1 ix bd cd dd ed fd dd hh ll ee ff ff 4 5 6 5 4 lda # opr lda opr lda opr lda opr ,x lda opr ,x lda ,x lda opr ,sp lda opr ,sp load a from m a (m) 0?? tt ? imm dir ext ix2 ix1 ix sp1 sp2 a6 b6 c6 d6 e6 f6 9ee6 9ed6 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 ldhx # opr ldhx opr load h:x from m h:x ( m:m + 1 ) 0?? tt ? imm dir 45 55 ii jj dd 3 4 ldx # opr ldx opr ldx opr ldx opr ,x ldx opr ,x ldx ,x ldx opr ,sp ldx opr ,sp load x from m x (m) 0?? tt ? imm dir ext ix2 ix1 ix sp1 sp2 ae be ce de ee fe 9eee 9ede ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 lsl opr lsla lslx lsl opr ,x lsl ,x lsl opr ,sp logical shift left (same as asl) t ?? ttt dir inh inh ix1 ix sp1 38 48 58 68 78 9e68 dd ff ff 4 1 1 4 3 5 table 6-1. instruction se t summary (sheet 5 of 9) source form operation description effect on ccr address mode opcode operand cycles vh i nzc c b0 b7 0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processor unit (cpu) instruction set summary mc68hc908jb8mc68hc08jb8mc68HC08JT8 ? rev. 2.1 technical data motorola central processor unit (cpu) 83 lsr opr lsra lsr x lsr opr ,x lsr ,x lsr opr ,sp logical shift right t ??0 tt dir inh inh ix1 ix sp1 34 44 54 64 74 9e64 dd ff ff 4 1 1 4 3 5 mov opr,opr mov opr, x+ mov # opr,opr mov x+ ,opr move (m) destination (m) source h:x (h:x) + 1 (ix+d, dix+) 0?? tt ? dd dix+ imd ix+d 4e 5e 6e 7e dd dd dd ii dd dd 5 4 4 4 mul unsigned multiply x:a (x) (a) ?0???0inh 42 5 neg opr nega negx neg opr ,x neg ,x neg opr ,sp negate (two?s complement) m ?(m) = $00 ? (m) a ?(a) = $00 ? (a) x ?(x) = $00 ? (x) m ?(m) = $00 ? (m) m ?(m) = $00 ? (m) t ?? ttt dir inh inh ix1 ix sp1 30 40 50 60 70 9e60 dd ff ff 4 1 1 4 3 5 nop no operation none ? ? ? ? ? ? inh 9d 1 nsa nibble swap a a (a[3:0]:a[7:4]) ? ? ? ? ? ? inh 62 3 ora # opr ora opr ora opr ora opr ,x ora opr ,x ora ,x ora opr ,sp ora opr ,sp inclusive or a and m a (a) | (m) 0 ? ? tt ? imm dir ext ix2 ix1 ix sp1 sp2 aa ba ca da ea fa 9eea 9eda ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 psha push a onto stack push (a); sp (sp) ? 1 ??????inh 87 2 pshh push h onto stack push (h); sp (sp) ? 1 ??????inh 8b 2 pshx push x onto stack push (x); sp (sp) ? 1 ??????inh 89 2 pula pull a from stack sp (sp + 1); pull ( a ) ??????inh 86 2 pulh pull h from stack sp (sp + 1); pull ( h ) ??????inh 8a 2 pulx pull x from stack sp (sp + 1); pull ( x ) ??????inh 88 2 rol opr rola rolx rol opr ,x rol ,x rol opr ,sp rotate left through carry t ?? ttt dir inh inh ix1 ix sp1 39 49 59 69 79 9e69 dd ff ff 4 1 1 4 3 5 table 6-1. instruction se t summary (sheet 6 of 9) source form operation description effect on ccr address mode opcode operand cycles vh i nzc b0 b7 c 0 c b0 b7 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processor unit (cpu) technical data mc68hc908jb8mc68h c08jb8mc68HC08JT8 ? rev. 2.1 84 central processor unit (cpu) motorola ror opr rora rorx ror opr ,x ror ,x ror opr ,sp rotate right through carry t ?? ttt dir inh inh ix1 ix sp1 36 46 56 66 76 9e66 dd ff ff 4 1 1 4 3 5 rsp reset stack pointer sp $ff ??????inh 9c 1 rti return from interrupt sp (sp) + 1; pull (ccr) sp (sp) + 1; pull (a) sp (sp) + 1; pull (x) sp (sp) + 1; pull (pch) sp (sp) + 1; pull (pcl) tttttt inh 80 7 rts return from subroutine sp sp + 1 ; pull ( pch) sp sp + 1; pull (pcl) ??????inh 81 4 sbc # opr sbc opr sbc opr sbc opr ,x sbc opr ,x sbc ,x sbc opr ,sp sbc opr ,sp subtract with carry a (a) ? (m) ? (c) t ?? ttt imm dir ext ix2 ix1 ix sp1 sp2 a2 b2 c2 d2 e2 f2 9ee2 9ed2 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 sec set carry bit c 1 ?????1inh 99 1 sei set interrupt mask i 1 ??1???inh 9b 2 sta opr sta opr sta opr ,x sta opr ,x sta ,x sta opr ,sp sta opr ,sp store a in m m (a) 0?? tt ? dir ext ix2 ix1 ix sp1 sp2 b7 c7 d7 e7 f7 9ee7 9ed7 dd hh ll ee ff ff ff ee ff 3 4 4 3 2 4 5 sthx opr store h:x in m (m:m + 1) (h:x) 0 ? ? tt ? dir 35 dd 4 stop enable irq pin; stop oscillator i 0; stop oscillator ? ? 0 ? ? ? inh 8e 1 stx opr stx opr stx opr ,x stx opr ,x stx ,x stx opr ,sp stx opr ,sp store x in m m (x) 0?? tt ? dir ext ix2 ix1 ix sp1 sp2 bf cf df ef ff 9eef 9edf dd hh ll ee ff ff ff ee ff 3 4 4 3 2 4 5 table 6-1. instruction se t summary (sheet 7 of 9) source form operation description effect on ccr address mode opcode operand cycles vh i nzc b0 b7 c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processor unit (cpu) instruction set summary mc68hc908jb8mc68hc08jb8mc68HC08JT8 ? rev. 2.1 technical data motorola central processor unit (cpu) 85 sub # opr sub opr sub opr sub opr ,x sub opr ,x sub ,x sub opr ,sp sub opr ,sp subtract a (a) ? (m) t ?? ttt imm dir ext ix2 ix1 ix sp1 sp2 a0 b0 c0 d0 e0 f0 9ee0 9ed0 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 swi software interrupt pc (pc) + 1; push (pcl) sp (sp) ? 1; push (pch) sp (sp) ? 1; push (x) sp (sp) ? 1; push (a) sp (sp) ? 1; push (ccr) sp (sp) ? 1; i 1 pch interrupt vector high byte pcl interrupt vector low byte ??1???inh 83 9 tap transfer a to ccr ccr (a) tttttt inh 84 2 tax transfer a to x x (a) ??????inh 97 1 tpa transfer ccr to a a (ccr) ? ? ? ? ? ? inh 85 1 tst opr tsta tstx tst opr ,x tst ,x tst opr ,sp test for negative or zero (a) ? $00 or (x) ? $00 or (m) ? $00 0 ? ? tt ? dir inh inh ix1 ix sp1 3d 4d 5d 6d 7d 9e6d dd ff ff 3 1 1 3 2 4 tsx transfer sp to h:x h:x (sp) + 1 ??????inh 95 2 txa transfer x to a a (x) ??????inh 9f 1 txs transfer h:x to sp (sp) (h:x) ? 1 ??????inh 94 2 table 6-1. instruction se t summary (sheet 8 of 9) source form operation description effect on ccr address mode opcode operand cycles vh i nzc f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processor unit (cpu) technical data mc68hc908jb8mc68h c08jb8mc68HC08JT8 ? rev. 2.1 86 central processor unit (cpu) motorola 6.9 opcode map see table 6-2 . a accumulator n any bit c carry/borrow bit opr operand (one or two bytes) ccr condition code register pc program counter dd direct address of operand pch program counter high byte dd rr direct address of operand and relative offset of branch instruction pcl program counter low byte dd direct to direct addressing mode rel relative addressing mode dir direct addressing mode rel relative program counter offset byte dix+ direct to indexed with post increment addressi ng mode rr relative program counter offset byte ee ff high and low bytes of offset in indexed, 16-bit offs et addressing sp1 stack pointer, 8-bit offset addressing mode ext extended addressing mode sp2 stack point er 16-bit offset addressing mode ff offset byte in indexed, 8-bit offset addressing sp stack pointer h half-carry bit u undefined h index register high byte v overflow bit hh ll high and low bytes of operand address in extended addressing x index register low byte i interrupt mask z zero bit ii immediate operand byte & logical and imd immediate source to direct destination addressing mode | logical or imm immediate addressing mode logical exclusive or inh inherent addressing mode ( ) contents of ix indexed, no offset addressing mode ?( ) negation (two?s complement) ix+ indexed, no offset, post increment addressing mode # immediate value ix+d indexed with post increm ent to direct addressing mode ? sign extend ix1 indexed, 8-bit offset addressing mode loaded with ix1+ indexed, 8-bit offset, post increment addressing mode ? if ix2 indexed, 16-bit offset addressing mode : concatenated with m memory location t set or cleared n negative bit ? not affected table 6-1. instruction se t summary (sheet 9 of 9) source form operation description effect on ccr address mode opcode operand cycles vh i nzc f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc908jb8mc68hc08jb8mc68HC08JT8 ? rev. 2.1 technical data motorola central processor unit (cpu) 87 central processor unit (cpu) opcode map table 6-2. opcode map bit manipulation branch read-modify-write control register/memory dir dir rel dir inh inh ix1 sp1 ix inh inh imm dir ext ix2 sp2 ix1 sp1 ix 0 1234569e6789abcd9ede9eef 0 5 brset0 3dir 4 bset0 2dir 3 bra 2rel 4 neg 2dir 1 nega 1inh 1 negx 1inh 4 neg 2ix1 5 neg 3sp1 3 neg 1ix 7 rti 1inh 3 bge 2rel 2 sub 2imm 3 sub 2dir 4 sub 3ext 4 sub 3ix2 5 sub 4sp2 3 sub 2ix1 4 sub 3sp1 2 sub 1ix 1 5 brclr0 3dir 4 bclr0 2dir 3 brn 2rel 5 cbeq 3dir 4 cbeqa 3imm 4 cbeqx 3imm 5 cbeq 3ix1+ 6 cbeq 4sp1 4 cbeq 2ix+ 4 rts 1inh 3 blt 2rel 2 cmp 2imm 3 cmp 2dir 4 cmp 3ext 4 cmp 3ix2 5 cmp 4sp2 3 cmp 2ix1 4 cmp 3sp1 2 cmp 1ix 2 5 brset1 3dir 4 bset1 2dir 3 bhi 2rel 5 mul 1inh 7 div 1inh 3 nsa 1inh 2 daa 1inh 3 bgt 2rel 2 sbc 2imm 3 sbc 2dir 4 sbc 3ext 4 sbc 3ix2 5 sbc 4sp2 3 sbc 2ix1 4 sbc 3sp1 2 sbc 1ix 3 5 brclr1 3dir 4 bclr1 2dir 3 bls 2rel 4 com 2dir 1 coma 1inh 1 comx 1inh 4 com 2ix1 5 com 3sp1 3 com 1ix 9 swi 1inh 3 ble 2rel 2 cpx 2imm 3 cpx 2dir 4 cpx 3ext 4 cpx 3ix2 5 cpx 4sp2 3 cpx 2ix1 4 cpx 3sp1 2 cpx 1ix 4 5 brset2 3dir 4 bset2 2dir 3 bcc 2rel 4 lsr 2dir 1 lsra 1inh 1 lsrx 1inh 4 lsr 2ix1 5 lsr 3sp1 3 lsr 1ix 2 ta p 1inh 2 txs 1inh 2 and 2imm 3 and 2dir 4 and 3ext 4 and 3ix2 5 and 4sp2 3 and 2ix1 4 and 3sp1 2 and 1ix 5 5 brclr2 3dir 4 bclr2 2dir 3 bcs 2rel 4 sthx 2dir 3 ldhx 3imm 4 ldhx 2dir 3 cphx 3imm 4 cphx 2dir 1 tpa 1inh 2 tsx 1inh 2 bit 2imm 3 bit 2dir 4 bit 3ext 4 bit 3ix2 5 bit 4sp2 3 bit 2ix1 4 bit 3sp1 2 bit 1ix 6 5 brset3 3dir 4 bset3 2dir 3 bne 2rel 4 ror 2dir 1 rora 1inh 1 rorx 1inh 4 ror 2ix1 5 ror 3sp1 3 ror 1ix 2 pula 1inh 2 lda 2imm 3 lda 2dir 4 lda 3ext 4 lda 3ix2 5 lda 4sp2 3 lda 2ix1 4 lda 3sp1 2 lda 1ix 7 5 brclr3 3dir 4 bclr3 2dir 3 beq 2rel 4 asr 2dir 1 asra 1inh 1 asrx 1inh 4 asr 2ix1 5 asr 3sp1 3 asr 1ix 2 psha 1inh 1 ta x 1inh 2 ais 2imm 3 sta 2dir 4 sta 3ext 4 sta 3ix2 5 sta 4sp2 3 sta 2ix1 4 sta 3sp1 2 sta 1ix 8 5 brset4 3dir 4 bset4 2dir 3 bhcc 2rel 4 lsl 2dir 1 lsla 1inh 1 lslx 1inh 4 lsl 2ix1 5 lsl 3sp1 3 lsl 1ix 2 pulx 1inh 1 clc 1inh 2 eor 2imm 3 eor 2dir 4 eor 3ext 4 eor 3ix2 5 eor 4sp2 3 eor 2ix1 4 eor 3sp1 2 eor 1ix 9 5 brclr4 3dir 4 bclr4 2dir 3 bhcs 2rel 4 rol 2dir 1 rola 1inh 1 rolx 1inh 4 rol 2ix1 5 rol 3sp1 3 rol 1ix 2 pshx 1inh 1 sec 1inh 2 adc 2imm 3 adc 2dir 4 adc 3ext 4 adc 3ix2 5 adc 4sp2 3 adc 2ix1 4 adc 3sp1 2 adc 1ix a 5 brset5 3dir 4 bset5 2dir 3 bpl 2rel 4 dec 2dir 1 deca 1inh 1 decx 1inh 4 dec 2ix1 5 dec 3sp1 3 dec 1ix 2 pulh 1inh 2 cli 1inh 2 ora 2imm 3 ora 2dir 4 ora 3ext 4 ora 3ix2 5 ora 4sp2 3 ora 2ix1 4 ora 3sp1 2 ora 1ix b 5 brclr5 3dir 4 bclr5 2dir 3 bmi 2rel 5 dbnz 3dir 3 dbnza 2inh 3 dbnzx 2inh 5 dbnz 3ix1 6 dbnz 4sp1 4 dbnz 2ix 2 pshh 1inh 2 sei 1inh 2 add 2imm 3 add 2dir 4 add 3ext 4 add 3ix2 5 add 4sp2 3 add 2ix1 4 add 3sp1 2 add 1ix c 5 brset6 3dir 4 bset6 2dir 3 bmc 2rel 4 inc 2dir 1 inca 1inh 1 incx 1inh 4 inc 2ix1 5 inc 3sp1 3 inc 1ix 1 clrh 1inh 1 rsp 1inh 2 jmp 2dir 3 jmp 3ext 4 jmp 3ix2 3 jmp 2ix1 2 jmp 1ix d 5 brclr6 3dir 4 bclr6 2dir 3 bms 2rel 3 tst 2dir 1 tsta 1inh 1 tstx 1inh 3 tst 2ix1 4 tst 3sp1 2 tst 1ix 1 nop 1inh 4 bsr 2rel 4 jsr 2dir 5 jsr 3ext 6 jsr 3ix2 5 jsr 2ix1 4 jsr 1ix e 5 brset7 3dir 4 bset7 2dir 3 bil 2rel 5 mov 3dd 4 mov 2dix+ 4 mov 3imd 4 mov 2ix+d 1 stop 1inh * 2 ldx 2imm 3 ldx 2dir 4 ldx 3ext 4 ldx 3ix2 5 ldx 4sp2 3 ldx 2ix1 4 ldx 3sp1 2 ldx 1ix f 5 brclr7 3dir 4 bclr7 2dir 3 bih 2rel 3 clr 2dir 1 clra 1inh 1 clrx 1inh 3 clr 2ix1 4 clr 3sp1 2 clr 1ix 1 wait 1inh 1 txa 1inh 2 aix 2imm 3 stx 2dir 4 stx 3ext 4 stx 3ix2 5 stx 4sp2 3 stx 2ix1 4 stx 3sp1 2 stx 1ix inh inherent rel relative sp1 stack pointer, 8-bit offset imm immediate ix indexed, no offset sp2 stack pointer, 16-bit offset dir direct ix1 indexed, 8-bit offset ix+ indexed, no offset with ext extended ix2 indexed, 16-bit offset post increment dd direct-direct imd immediate-direct ix1+ indexed, 1-byte offset with ix+d indexed-direct dix+ direct-indexed post increment * pre-byte for stack pointer indexed instructions 0 high byte of opcode in hexadecimal low byte of opcode in hexadecimal 0 5 brset0 3dir cycles opcode mnemonic number of bytes / addressing mode msb lsb msb lsb f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processor unit (cpu) technical data mc68hc908jb8mc68h c08jb8mc68HC08JT8 ? rev. 2.1 88 central processor unit (cpu) motorola f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc908jb8mc68hc08jb8mc68HC08JT8 ? rev. 2.1 technical data motorola oscillator (osc) 89 technical data ? mc68hc908jb8?mc68hc08jb8?mc68HC08JT8 section 7. oscillator (osc) 7.1 contents 7.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 7.3 oscillator external connecti ons . . . . . . . . . . . . . . . . . . . . . . . .90 7.4 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 7.4.1 crystal amplifier input pin (osc1). . . . . . . . . . . . . . . . . . . . 91 7.4.2 crystal amplifier out put pin (osc2) . . . . . . . . . . . . . . . . . . 91 7.4.3 oscillator enable signal (simoscen). . . . . . . . . . . . . . . . . 91 7.4.4 external clock source (oscxclk) . . . . . . . . . . . . . . . . . . . 91 7.4.5 oscillator out (oscout). . . . . . . . . . . . . . . . . . . . . . . . . . . 92 7.5 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 7.5.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92 7.5.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92 7.6 oscillator during break mode . . . . . . . . . . . . . . . . . . . . . . . . . . 92 7.2 introduction the oscillator circuit is designed for use with crystals or ceramic resonators. the oscillator circuit gen erates the crystal clock signal. the crystal oscillator out put signal passes thro ugh the clock doubler. oscxclk is the output signal of the clock doubl er. oscxclk is divided by two before being passed on to t he system integrat ion module (sim) for bus clo ck generation. figure 7-1 shows the structure of the oscillator. the oscillator requires various external components. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . oscillator (osc) technical data mc68hc908jb8mc68h c08jb8mc68HC08JT8 ? rev. 2.1 90 oscillator (osc) motorola 7.3 oscillator ex ternal connections in its typical configur ation, the oscillator requires five external components. the crystal oscillator is normally connected in a pierce oscillator configuration, as shown in figure 7-1 . this figure shows only the logical representat ion of the internal components and may not represent actual circui try. the oscillator conf iguration uses five components: crystal, x 1 fixed capacitor, c 1 tuning capacitor, c 2 (can also be a fixed capacitor) feedback resistor, r b series resistor, r s (optional) figure 7-1. oscillator external connections c1 c2 simoscen oscxclk x1 r s * * r s can be 0 (shorted) when used with mcu from sim oscout to usb to sim clock doubler 2 to sim osc1 osc2 r b higher frequency crystals. refer to manufacturer?s data. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . oscillator (osc) i/o signals mc68hc908jb8mc68hc08jb8mc68HC08JT8 ? rev. 2.1 technical data motorola oscillator (osc) 91 the series resistor (r s ) is included in the diagram to follow strict pierce oscillator guidelines and may not be r equired for all rang es of operation, especially with high-frequency cr ystals. refer to the crystal manufacturer?s data for more information. 7.4 i/o signals the following paragraphs describe the oscillator input/output (i/o) signals. 7.4.1 crystal amplifier input pin (osc1) the osc1 pin is an input to the crystal oscillator amplifier. 7.4.2 crystal amplifier output pin (osc2) the osc2 pin is the output of the crystal oscillator inverting amplifier. 7.4.3 oscillator enable signal (simoscen) the simoscen signal come s from the system int egration module (sim) and enables the oscillator. 7.4.4 external clock source (oscxclk) the crystal oscillator output signal passes through the clock doubler and oscxclk is the output signal of the clock doubl er. oscxclk runs at twice the speed of the crystal (f xclk ). figure 7-1 shows only the logical relation of oscxclk to osc1 and osc2 and may not represent the actual circuitry. the duty cycl e of oscxclk is unknown and may depend on the crystal and ot her external factors. also, the frequency and amplitude of oscxclk can be unstable at startup. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . oscillator (osc) technical data mc68hc908jb8mc68h c08jb8mc68HC08JT8 ? rev. 2.1 92 oscillator (osc) motorola 7.4.5 oscillator out (oscout) the clock driven to the si m is oscxclk. this signal is driven to the sim for generation of the bus clocks used by the c pu and other modules on the mcu. oscout will be divided again in the sim and results in the internal bus frequency being one fort h of the oscxclk frequency or one half of the crystal frequency. 7.5 low-power modes the wait and stop in structions put the mcu in low-power- consumption standby modes. 7.5.1 wait mode the wait instruction has no effect on the osci llator logic. oscxclk continues to drive to the sim module. 7.5.2 stop mode the stop instructio n disables the oscxclk output. 7.6 oscillator during break mode the oscillator continue s to drive oscxclk wh en the chip enters the break state. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc908jb8mc68hc08jb8mc68HC08JT8 ? rev. 2.1 technical data motorola system integration module (sim) 93 technical data ? mc68hc908jb8?mc68hc08jb8?mc68HC08JT8 section 8. system integration module (sim) 8.1 contents 8.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 8.3 sim bus clock control and generation . . . . . . . . . . . . . . . . . . 96 8.3.1 bus timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 8.3.2 clock startup from po r or lvi reset . . . . . . . . . . . . . . . . . 97 8.3.3 clocks in stop mode and wait mode . . . . . . . . . . . . . . . . . . 97 8.4 reset and system initializa tion. . . . . . . . . . . . . . . . . . . . . . . . . 97 8.4.1 external pin reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 8.4.2 active resets from inte rnal sources . . . . . . . . . . . . . . . . . . 99 8.4.2.1 power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100 8.4.2.2 computer operati ng properly (cop) rese t. . . . . . . . . . 101 8.4.2.3 illegal opcode reset . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 8.4.2.4 illegal address reset . . . . . . . . . . . . . . . . . . . . . . . . . . .101 8.4.2.5 low-voltage inhibit (lvi) reset . . . . . . . . . . . . . . . . . . . 102 8.4.2.6 universal serial bu s reset . . . . . . . . . . . . . . . . . . . . . . 102 8.4.2.7 registers values after different resets. . . . . . . . . . . . . 102 8.5 sim counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 8.5.1 sim counter during power-on rese t . . . . . . . . . . . . . . . . 103 8.5.2 sim counter during stop mode re covery . . . . . . . . . . . . . 104 8.5.3 sim counter and reset states. . . . . . . . . . . . . . . . . . . . . . 104 8.6 exception control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104 8.6.1 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 8.6.1.1 hardware interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 8.6.1.2 swi instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 8.6.2 interrupt status regist ers. . . . . . . . . . . . . . . . . . . . . . . . . . 108 8.6.2.1 interrupt stat us register 1 . . . . . . . . . . . . . . . . . . . . . . . 109 8.6.3 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 8.6.4 break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 8.6.5 status flag protection in break mode . . . . . . . . . . . . . . . . 110 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) technical data mc68hc908jb8mc68h c08jb8mc68HC08JT8 ? rev. 2.1 94 system integration module (sim) motorola 8.7 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 8.7.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110 8.7.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112 8.8 sim registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 8.8.1 break status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 8.8.2 reset status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 8.8.3 break flag control regi ster . . . . . . . . . . . . . . . . . . . . . . .116 8.2 introduction this section describes the system integration module (sim), which supports up to 8 external and/or inte rnal interrupts. together with the cpu, the sim controls all mcu ac tivities. the sim is a system state controller that coordi nates cpu and exception ti ming. a block diagram of the sim is shown in figure 8-1 . figure 8-2 is a summar y of the sim i/o registers. the sim is responsible for: bus clock generation and cont rol for cpu and peripherals ? stop/wait/reset/bre ak entry and recovery ? internal clock control master reset control, includi ng power-on reset (por) and cop timeout interrupt control: ? acknowledge timing ? arbitration control timing ? vector address generation cpu enable/disable timing modular architecture exp andable to 128 interrupt sources f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) introduction mc68hc908jb8mc68hc08jb8mc68HC08JT8 ? rev. 2.1 technical data motorola system integration module (sim) 95 figure 8-1. sim block diagram table 8-1. sim module signal name conventions signal name description oscxclk clock doubler output which has twice the frequency of osc1 from the oscillator oscout the oscxclk frequency divided by two. this signal is again divided by two in the sim to generate the internal bus clocks. (bus clock = oscxclk 4 = f osc 2) iab internal address bus idb internal data bus porrst signal from the power-on reset module to the sim irst internal reset signal r/w read/write signal stop/wait clock control clock generators por control reset pin control sim reset status register interrupt control and priority decode module stop module wait cpu stop (from cpu) cpu wait (from cpu) simoscen (to oscillator) oscout (from clock doubler) internal clocks master reset control reset pin logic illegal opcode (from cpu) illegal address (from address map decoders) cop timeout (from cop module) interrupt sources cpu interface reset control sim counter cop clock oscxclk (from clock doubler) 2 usb reset (from usb module) lvi reset (from lvi module) vdd internal pull-up f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) technical data mc68hc908jb8mc68h c08jb8mc68HC08JT8 ? rev. 2.1 96 system integration module (sim) motorola 8.3 sim bus clock control and generation the bus clock generator provides system clock signal s for the cpu and peripherals on the mcu. the syst em clocks are generated from an incoming clock, oscout, as shown in figure 8-3 . figure 8-3. sim clock signals addr.register name bit 7654321bit 0 $fe00 break status register (bsr) read: rrrrrr sbsw r write: see note reset: 0 note: writing a logic 0 clears sbsw. $fe01 reset status register (rsr) read: por pin cop ilop ilad usb lvi 0 write: por:10000000 $fe02 reserved read: rrrrrrrr write: $fe03 break flag control register (bfcr) read: bcferrrrrrr write: reset: 0 $fe04 interrupt status register 1 (int1) read: if6 if5 if4 if3 if2 if1 0 0 write:rrrrrrrr reset:00000000 figure 8-2. sim i/o register summary 2 bus clock generators sim sim counter from clock doubler from clock doubler oscout oscxclk f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) reset and system initialization mc68hc908jb8mc68hc08jb8mc68HC08JT8 ? rev. 2.1 technical data motorola system integration module (sim) 97 8.3.1 bus timing in user mode , the internal bus frequency is the o scillator frequency divided by two. 8.3.2 clock startup from por or lvi reset when the power-on reset (por) modu le or the low-voltage inhibit module generates a reset, the clocks to the cpu and peripherals are inactive and held in an inactive phase until after the 4096 oscxclk cycle por timeout has completed. the rst pin is driven low by the sim during this entire period. the ibus cl ocks start upon completion of the timeout. 8.3.3 clocks in stop mode and wait mode upon exit from stop mode by an interr upt, break, or rese t, the sim allows oscxclk to clock the sim counter . the cpu and peripheral clocks do not become active until after the stop delay timeout. this timeout is selectable as 4096 or 2 048 oscxclk cycles. (see 8.7.2 stop mode .) in wait mode, t he cpu clocks are inactive. th e sim also produces two sets of clocks for other modules. refer to the wait mode subsection of each module to see if t he module is active or i nactive in wait mode. some modules can be programmed to be active in wait mode. 8.4 reset and system initialization the mcu has these reset sources: power-on reset module (por) external reset pin (rst ) computer operating pr operly module (cop) illegal opcode illegal address universal serial bus module (usb) low-voltage inhi bit module (lvi) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) technical data mc68hc908jb8mc68h c08jb8mc68HC08JT8 ? rev. 2.1 98 system integration module (sim) motorola all of these resets produce the vector $fffe?ffff ($fefe?feff in monitor mode) and assert the internal reset signal (irst). irst causes all registers to be returned to thei r default values and all modules to be returned to thei r reset states. an internal reset clear s the sim counter (see 8.5 sim counter ), but an external reset does not. each of th e resets sets a co rresponding bit in the reset status regi ster (rsr). (see 8.8 sim registers .) 8.4.1 external pin reset the rst pin circuit includes an internal pullup device. pulling the asynchronous rst pin low halts all processing. the pin bit of the reset status register (rsr) is set as long as rst is held low for a minimum of 67 oscxclk cycles, assuming that nei ther the por nor the lvi was the source of the reset. see table 8-2 for details. figure 8-4 shows the relative timing. figure 8-4. extern al reset timing table 8-2. pin bit set timing reset type number of cycles required to set pin por/lvi 4163 (4096 + 64 + 3) all others 67 (64 + 3) rst iab pc vect h vect l oscout f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) reset and system initialization mc68hc908jb8mc68hc08jb8mc68HC08JT8 ? rev. 2.1 technical data motorola system integration module (sim) 99 8.4.2 active resets from internal sources all internal reset sour ces actively pull the rst pin low for 32 oscxclk cycles to allow resetting of external peripherals. the inte rnal reset signal irst continues to be asserted for an additional 32 cycl es. (see figure 8-5.) an internal reset can be c aused by an illegal address, illegal opcode, cop timeout, lvi, t he usb module or por. (see figure 8-6 . sources of internal reset .) note: for lvi or por resets , the sim cycles through 4096 oscxclk cycles during which the si m forces the rst pin low. the internal reset signal then follows the sequence fr om the falling edge of rst shown in figure 8-5 . figure 8-5. inter nal reset timing the cop reset is asynchro nous to the bus clock. figure 8-6. sources of internal reset the active reset feature allows the par t to issue a reset to peripherals and other chips within a system built around the mcu. irst rst rst pulled low by mcu iab 32 cycles 32 cycles vector high oscxclk illegal address rst illegal opcode rst coprst por internal reset lvi usb f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) technical data mc68hc908jb8mc68h c08jb8mc68HC08JT8 ? rev. 2.1 100 system integration module (sim) motorola 8.4.2.1 power-on reset when power is first applied to the mcu, the power-on reset module (por) generates a pul se to indicate that pow er-on has occurred. the external reset pin (rst ) is held low while the sim counter counts out 4096 oscxclk cycles. sixty-four osc xclk cycles later, the cpu and memories are released from reset to allow the reset vector sequence to occur. at power-on, the foll owing events occur: a por pulse is generated. the internal reset signal is asserted. the sim enables the oscill ator to drive oscxclk. internal clocks to the cpu and m odules are held i nactive for 4096 oscxclk cycles to allow stab ilization of t he oscillator. the rst pin is driven low during th e oscillator stabilization time. the por bit of the reset status re gister (rsr) is set and all other bits in the register are cleared. figure 8-7. por recovery porrst osc1 oscxclk oscout rst iab 4096 cycles 32 cycles 32 cycles $fffe $ffff f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) reset and system initialization mc68hc908jb8mc68hc08jb8mc68HC08JT8 ? rev. 2.1 technical data motorola system integration module (sim) 101 8.4.2.2 computer operat ing properly (cop) reset an input to the sim is reserved for the cop reset signal. the overflow of the cop counter causes an internal reset and sets the cop bit in the reset status register (rsr). th e sim actively pulls down the rst pin for all internal reset sources. to prevent a cop module timeout, wr ite any value to location $ffff. writing to location $ffff clears the cop counter and stages 12 through 5 of the sim counter. the sim counter output, which occurs at least every 2 12 ? 2 4 oscxclk cycles, drives the cop counter. the cop should be serviced as s oon as possible out of reset to guarantee the maximum amount of time before the first timeout. the cop module is disabled if the rst pin or the irq pin is held at v dd +v hi while the mcu is in monito r mode. the cop module can be disabled only through co mbinational logic c onditioned with the high voltage signal on the rst or the irq pin. this prevent s the cop from becoming disabled as a result of ex ternal noise. duri ng a break state, v dd +v hi on the rst pin disables the cop module. 8.4.2.3 illegal opcode reset the sim decodes signals from the cpu to detect illegal instructions. an illegal instruction sets t he ilop bit in the reset st atus register (rsr) and causes a reset. if the stop enable bit, st op, in the mask option regi ster is logic 0, the sim treats the stop instruction as an illegal opcode and causes an illegal opcode reset. the sim actively pulls down the rst pin for all internal reset sources. 8.4.2.4 illegal address reset an opcode fetch from an unm apped address genera tes an illegal address reset. the sim ve rifies that t he cpu is fetching an opcode prior to asserting the ilad bit in the reset stat us register (rsr) and resetting the mcu. a data fetch from an unmapped addre ss does not generate a reset. the sim active ly pulls down the rst pin for all internal reset sources. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) technical data mc68hc908jb8mc68h c08jb8mc68HC08JT8 ? rev. 2.1 102 system integration module (sim) motorola 8.4.2.5 low-voltage inhibit (lvi) reset the low-voltage inhibit m odule (lvi) asserts its output to the sim when the v dd voltage falls to t he lvi reset voltage, v trip . the lvi bit in the reset status register (rsr) is se t, and the external reset pin (rst ) is held low while the sim counter counts out 4096 oscxclk cycles. sixty-four oscxclk cycles later, the cpu is released from re set to allow the reset vector sequence to occur. the sim actively pulls down the rst pin for all internal reset sources. 8.4.2.6 universal serial bus reset the usb module will de tect a reset signaled on t he bus by the presence of an extended se0 at t he usb data pins of a device. the mcu seeing a single-ended 0 on it s usb data inputs for more than 2.5 s treats that signal as a reset. after the reset is removed, the device will be in the attached, but not yet addressed or conf igured, state (refer to section 9.1 usb devices of the universal serial bus specification rev. 1.1). the device must be able to accept t he device address via a set_address command (refer to se ction 9.4 of the universal serial bus specification rev. 1.1) no later than 10ms after the reset is removed. usb reset can be disabled to generate an internal reset, instead, a usb interrupt can be generated. (see section 5. confi guration register (config) .) note: usb reset is disabled when the usb module is disabled by clearing the usben bit of t he usb address r egister (uaddr). 8.4.2.7 registers values after different resets some registers are reset by por or lvi reset only. table 8-3 shows the registers or register bits which are unaffect ed by normal resets. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) sim counter mc68hc908jb8mc68hc08jb8mc68HC08JT8 ? rev. 2.1 technical data motorola system integration module (sim) 103 8.5 sim counter the sim counter is used by the pow er-on reset module (por) and in stop mode recovery to allow the os cillator time to stabilize before enabling the internal bus (i bus) clocks. the sim c ounter also serves as a prescalar for the computer operati ng properly module (cop). the sim counter uses 12 stages for counting, followed by a 13th stage that triggers a reset of sim counters and supplies the cl ock for the cop module. the sim counter is clo cked by the falli ng edge of oscxclk. 8.5.1 sim counter during power-on reset the power-on reset module (por) dete cts power appli ed to the mcu. at power-on, the por ci rcuit asserts the signal porrst. once the sim is initialized, it enables the oscillator to drive the bus clock state machine. table 8-3. registers not affected by normal reset bits registers after reset (except por or lvi) after por or lvi urstd, lvidis config unaffected 0 usben uaddr unaffected 0 pullen ucr3 unaffected 0 all usr0, usr1 unaffected indeterminate all ue0d0?ue0d7 unaffected indeterminate all ue1d0?ue1d7 unaffected indeterminate all ue2d0?ue2d7 unaffected indeterminate all pta, ptb, ptc, ptd, and pte unaffected indeterminate ddra7 ddra unaffected 0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) technical data mc68hc908jb8mc68h c08jb8mc68HC08JT8 ? rev. 2.1 104 system integration module (sim) motorola 8.5.2 sim counter during stop mode recovery the sim counter also is used for stop mode recovery. the stop instruction clears the sim counter. af ter an interrupt, brea k, or reset, the sim senses the state of the short stop recovery bit, ssrec, in the configuration register (c onfig). if the ssrec bit is a logic 1, then the stop recovery is reduced from the normal delay of 4096 oscxclk cycles down to 2048 osc xclk cycles. this is id eal for applications using canned oscillators that do not require long startup times from stop mode. external crystal applications should use the full stop recovery time, that is, with ssre c cleared in the configur ation register (config). 8.5.3 sim counter and reset states external reset has no effect on the sim counter. (see 8.7.2 stop mode for details.) the sim counter is free -running after all re set states. (see 8.4.2 active resets from internal sources for counter control and internal reset re covery sequences.) 8.6 exception control normal, sequential progra m execution can be chang ed in three different ways: interrupts ? maskable hardware cpu interrupts ? non-maskable software interrupt instruction (swi) reset break interrupts 8.6.1 interrupts an interrupt temporarily changes th e sequence of program execution to respond to a parti cular event. figure 8-8 flow charts the handling of system interrupts. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) exception control mc68hc908jb8mc68hc08jb8mc68HC08JT8 ? rev. 2.1 technical data motorola system integration module (sim) 105 figure 8-8. interrupt processing no no no yes no no yes no yes yes from reset break i bit set? irq interrupt usb interrupt fetch next instruction unstack cpu registers stack cpu registers set i bit load pc with interrupt vector execute instruction yes yes i bit set? interrupt yes other interrupts no swi instruction rti instruction ? ? ? ? ? ? f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) technical data mc68hc908jb8mc68h c08jb8mc68HC08JT8 ? rev. 2.1 106 system integration module (sim) motorola interrupts are latched and arbitration is performed in the sim at the start of interrupt processing. the arbitration result is a constant that the cpu uses to determine which ve ctor to fetch. once an interrupt is latched by the sim, no other interrupt can take precedence, regardless of priority, until the latched interrupt is serv iced or the i bit is cleared. at the beginning of an interrupt, the cpu sa ves the cpu register contents on the sta ck and sets the interrupt ma sk (i bit) to prevent additional interrupts. at the end of an interrupt , the rti instruction recovers the cpu regist er contents from the stack so that normal processing can resume. figure 8-9 shows interrupt entry timing. figure 8-10 shows interrupt recovery timing. figure 8-9. interrupt entry figure 8-10. in terrupt recovery module idb r/w interrupt dummy sp sp ? 1 sp ? 2 sp ? 3 sp ? 4 vect h vect l start addr iab dummy pc ? 1[7:0] pc ? 1[15:8] x a ccr v data h v data l opcode i bit module idb r/w interrupt sp ? 4 sp ? 3 sp ? 2 sp ? 1 sp pc pc + 1 iab ccr a x pc ?1 [15:8] pc ? 1[7:0] opcode operand i bit f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) exception control mc68hc908jb8mc68hc08jb8mc68HC08JT8 ? rev. 2.1 technical data motorola system integration module (sim) 107 8.6.1.1 hardware interrupts a hardware interrupt does not stop the current in struction. processing of a hardware interrupt begins after completion of t he current instruction. when the current instruction is complete, the sim checks all pending hardware interrupts. if interrupts ar e not masked (i bit clear in the condition code register) and if the corresponding interrupt enable bit is set, the sim proceeds with interrup t processing; other wise, the next instruction is fetched and executed. if more than one interrupt is pending at th e end of an instruction execution, the highest priority interrupt is serviced first. figure 8-11 demonstrates what hap pens when two interrupts are pending. if an interrupt is pending upon exit from the original inte rrupt service routine, the pending interrupt is serviced before the lda in struction is executed. figure 8-11 . interrupt recognition example the lda opcode is pr efetched by both th e int1 and int2 rti instructions. however, in the case of the int1 rti prefetch, this is a redundant operation. note: to maintain compatibility with the m6805 family, the h register is not pushed on the stack during in terrupt entry. if the in terrupt service routine modifies the h register or uses the indexed addressing mode, software should save the h register and then restore it prio r to exiting the routine. cli lda int1 pulh rti int2 background #$ff pshh int1 interrupt service routine pulh rti pshh int2 interrupt service routine routine f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) technical data mc68hc908jb8mc68h c08jb8mc68HC08JT8 ? rev. 2.1 108 system integration module (sim) motorola 8.6.1.2 swi instruction the swi instruction is a non-maskable instruct ion that causes an interrupt regardless of the state of the interrupt mask (i bit) in the condition code register. note: a software interrupt pushes pc onto the stack. a software interrupt does not push pc?1, as a har dware interrupt does. 8.6.2 interrupt status registers the flags in the interrupt status re gisters identify maskable interrupt sources. table 8-4 summarizes the interrupt sources and the interrupt status register flags that they set. the interrupt status registers can be useful for debugging. table 8-4. interrupt sources source flags mask (1) int register flag priority (2) vector address swi instruction ? 0 $fffc?$fffd usb reset interrupt rstf urstd if2 1 $fffa?$fffb usb endpoint 0 transmit txd0f txd0ie usb endpoint 0 receive rxd0f rxd0ie usb endpoint 1 transmit txd1f txd1ie usb endpoint 2 transmit txd2f txd2ie usb endpoint 2 receive rxd2f rxd2ie usb end of packet eopf eopie usb resume interrupt resumf ? irq interrupt (irq , pte4) irqf pte4if imask if1 2 $fff8?$fff9 tim channel 0 ch0f ch0ie if3 3 $fff6?$fff7 tim channel 1 ch1f ch1ie if4 4 $fff4?$fff5 tim overflow tof toie if5 5 $fff2?$fff3 keyboard interrupt keyf imaskk if6 6 $fff0?$fff1 1. the i bit in the condition code register is a global mask for all interrupt sources except the swi instruction. 2. 0 = highest priority f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) exception control mc68hc908jb8mc68hc08jb8mc68HC08JT8 ? rev. 2.1 technical data motorola system integration module (sim) 109 8.6.2.1 interrupt status register 1 if6?if1 ? interrupt flags 1?6 these flags indicate the presence of interrupt r equests from the sources shown in table 8-4 . 1 = interrupt request present 0 = no interrupt request present bit 0 and bit 1 ? always read 0 8.6.3 reset all reset sources always have equal and highest pr iority and cannot be arbitrated. 8.6.4 break interrupts the break module can st op normal program flow at a software- programmable break point by asserti ng its break interrupt output. (see section 17. break module (break) .) the sim puts t he cpu into the break state by forcing it to the swi vector loca tion. refer to the break interrupt subsection of each module to see how each module is affected by the break state. address: $fe04 bit 7654321bit 0 read: if6 if5 if4 if3 if2 if1 0 0 write:rrrrrrrr reset:00000000 r=reserved figure 8-12. interrupt st atus register 1 (int1) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) technical data mc68hc908jb8mc68h c08jb8mc68HC08JT8 ? rev. 2.1 110 system integration module (sim) motorola 8.6.5 status flag protection in break mode the sim controls whether status fl ags contained in ot her modules can be cleared during break m ode. the user can sele ct whether flags are protected from being clea red by properly initiali zing the break clear flag enable bit (bcfe) in the break flag contro l register (bfcr). protecting flags in break mode ensures that set flags will not be cleared while in break mode. this protection allows registers to be freely read and written during break mo de without losing stat us flag information. setting the bcfe bit e nables the clearing mechani sms. once cleared in break mode, a flag remains cleared even when break mode is exited. status flags with a 2- step clearing mechanism ? for example, a read of one register followed by the read or write of a nother ? are protected, even when the first step is accomplished prior to entering break mode. upon leaving break mode, execution of the second step will clear the flag as normal. 8.7 low-power modes executing the wait or stop instruction puts t he mcu in a low-power- consumption mode for st andby situations. the s im holds the cpu in a non-clocked state. the operation of eac h of these mode s is described here. both stop and wait clear the interrupt mask (i) in the condition code register, allowing interrupts to occur. 8.7.1 wait mode in wait mode, t he cpu clocks are inactive while the peripheral clocks continue to run. figure 8-13 shows the timing fo r wait mode entry. a module that is active during wa it mode can wake up the cpu with an interrupt if the interrupt is enabled . stacking for the interrupt begins one cycle after the wait instruction duri ng which the interr upt occurred. in wait mode, the cpu clocks are i nactive. refer to the wait mode subsection of each module to see if th e module is active or inactive in wait mode. some modules can be programmed to be active in wait mode. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) low-power modes mc68hc908jb8mc68hc08jb8mc68HC08JT8 ? rev. 2.1 technical data motorola system integration module (sim) 111 wait mode can also be exited by a reset or break. a break interrupt during wait mode sets the sim break stop/wait bit, sbsw , in the break status register (bsr). if the cop disable bit, co pd, in the mask option register is logic 0, then the comp uter operating pr operly module (cop) is enabled and remains active in wait mode. figure 8-13. wait mode entry timing figure 8-14 and figure 8-15 show the timing for wait recovery. figure 8-14. wait recovery from interrupt or break figure 8-15. wait recover y from internal reset wait addr + 1 same same iab idb previous data next opcode same wait addr same r/w note: previous data can be operand data or the wait opcode, depending on the last instruction. $6e0c $6e0b $00ff $00fe $00fd $00fc $a6 $a6 $01 $0b $6e $a6 iab idb exitstopwait note: exitstopwait = rst pin or cpu interrupt or break interrupt iab idb rst $a6 $a6 $6e0b rst vct h rst vct l $a6 oscxclk 32 cycles 32 cycles f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) technical data mc68hc908jb8mc68h c08jb8mc68HC08JT8 ? rev. 2.1 112 system integration module (sim) motorola 8.7.2 stop mode in stop mode, the sim counter is reset and the system clocks are disabled. an interrupt request from a module can cause an exit from stop mode. stacking for inte rrupts begins after the selected stop recovery time has elapsed. reset or break al so causes an exit from stop mode. the sim disables the oscillator si gnals (oscout and oscxclk) in stop mode, stopping the cpu and peripherals. stop recovery time is selectable using the ssrec bit in the configurati on register (config). if ssrec is set, stop recovery is r educed from the nor mal delay of 4096 oscxclk cycles down to 2048. this is ideal for applications using canned oscillators that do not require long start up times from stop mode. note: external crystal applicati ons should use the full stop recovery time by clearing the ssrec bit. a break interrupt during stop mode sets the si m break stop/wait bit (sbsw) in the break st atus register (bsr). the sim counter is held in reset from the execution of the stop instruction until th e beginning of stop recovery. it is then used to time the recovery period. figure 8-16 shows stop mode entry timing. note: to minimize stop current, all pins configured as i nputs should be driven to a logic 1 or logic 0. figure 8-16. stop mode entry timing stop addr + 1 same same iab idb previous data next opcode same stop addr same r/w cpustop note: previous data can be operand data or the stop opcode, depending on the last instruction. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) sim registers mc68hc908jb8mc68hc08jb8mc68HC08JT8 ? rev. 2.1 technical data motorola system integration module (sim) 113 figure 8-17. stop mode recovery from interrupt or break 8.8 sim registers the sim has two break regist ers and one reset register. 8.8.1 break status register the break status register contains a flag to indicate that a break caused an exit from stop or wait mode. sbsw ? sim break stop/wait this status bit is useful in applications requiring a return to wait or stop mode after exiting from a break interrupt. clear sbsw by writing a logic 0 to it. re set clears sbsw. 1 = stop mode or wa it mode was exited by break interrupt 0 = stop mode or wait mode was not exited by break interrupt oscxclk int/break iab stop + 2 stop + 2 sp sp ? 1 sp ? 2 sp ? 3 stop +1 stop recovery period address: $fe00 bit 7654321bit 0 read: rrrrrr sbsw r write: note 1 reset: 0 note 1. writing a logic 0 clears sbsw. r = reserved figure 8-18. break stat us register (bsr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) technical data mc68hc908jb8mc68h c08jb8mc68HC08JT8 ? rev. 2.1 114 system integration module (sim) motorola sbsw can be read within the break state swi routi ne. the user can modify the return address on the st ack by subtractin g one from it. the following code is an example of th is. writing 0 to the sbsw bit clears it. 8.8.2 reset status register this register contains sev en flags that show the sour ce of the last reset. all flag bits are cleared aut omatically following a r ead of the register. the register is initialized on power-up as shown with the por bit set and all other bits cleared. however, during a por or any other internal reset, the rst pin is pulled low. after the pin is released, it will be sampled 32 xclk cycles later. if the pin is not above a v ih at that time, then the pin bit in the rsr may be set in addition to whatever other bits are set. this code works if the h regi ster has been pushed onto the stack in the break service routine software. this code should be executed at the end of the break service routine software. hibyte equ 5 lobyte equ 6 ; if not sbsw, do rti brclr sbsw,bsr, return ; ; see if wait mode or stop mode was exited by break. tst lobyte,sp ; if returnlo is not zero, bne dolo ; then just decrement low byte. dec hibyte,sp ; else deal with high byte, too. dolo dec lobyte,sp ; point to wait/stop opcode. return pulh rti ; restore h register. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) sim registers mc68hc908jb8mc68hc08jb8mc68HC08JT8 ? rev. 2.1 technical data motorola system integration module (sim) 115 por ? power-on reset bit 1 = a por has occurred 0 = read of rsr pin ? external reset bit 1 = an external reset has occurred since the last read of the rsr 0 = read of rsr cop ? computer operati ng properly reset bit 1 = a cop reset has o ccurred since the last read of the rsr 0 = por or read of rsr ilop ? illegal opcode reset bit an illegal opcode reset has occurred since the la st read of the rsr 0 = por or read of rsr ilad ? illegal address rese t bit (opcode fetches only) 1 = an illegal address reset has o ccurred since the last read of the rsr 0 = por or read of rsr usb ? universal serial bus reset bit 1 = last reset caused by the usb module 0 = por or read of rsr lvi ? low voltage inhibit reset bit 1 = a lvi reset has occurred si nce the last read of psr 0 = por or read of rsr address: $fe01 bit 7654321bit 0 read: por pin cop ilop ilad usb lvi 0 write: por: 10000000 = unimplemented figure 8-19. reset st atus register (rsr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) technical data mc68hc908jb8mc68h c08jb8mc68HC08JT8 ? rev. 2.1 116 system integration module (sim) motorola 8.8.3 break flag control register the break control register contains a bit that enables so ftware to clear status bits while the mc u is in a break state. bcfe ? break clear flag enable bit this read/write bit enables software to clear st atus bits by accessing status registers while the mcu is in a break state. to clear status bits during the break state, t he bcfe bit must be set. 1 = status bits clearable during break 0 = status bits not clearable during break address: $fe03 bit 7654321bit 0 read: bcferrrrrrr write: por: 0 r = reserved figure 8-20. break flag c ontrol register (bfcr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc908jb8mc68hc08jb8mc68HC08JT8 ? rev. 2.1 technical data motorola universal serial bus module (usb) 117 technical data ? mc68hc908jb8?mc68hc08jb8?mc68HC08JT8 section 9. universal serial bus module (usb) 9.1 contents 9.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 9.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 9.4 pin name conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 9.5 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .124 9.5.1 usb protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 9.5.1.1 sync pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 9.5.1.2 packet identifier fiel d . . . . . . . . . . . . . . . . . . . . . . . . . . 127 9.5.1.3 address field (addr) . . . . . . . . . . . . . . . . . . . . . . . . . . 128 9.5.1.4 endpoint field (endp) . . . . . . . . . . . . . . . . . . . . . . . . . . 128 9.5.1.5 cyclic redundancy c heck (crc) . . . . . . . . . . . . . . . . . 128 9.5.1.6 end-of-packet (eop) . . . . . . . . . . . . . . . . . . . . . . . . . . .128 9.5.2 reset signaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 9.5.3 suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 9.5.4 resume after suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 9.5.4.1 host initiated resume . . . . . . . . . . . . . . . . . . . . . . . . . . 131 9.5.4.2 usb reset signalling. . . . . . . . . . . . . . . . . . . . . . . . . . .131 9.5.4.3 remote wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131 9.5.5 low-speed device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 9.6 clock requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 9.7 hardware description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 9.7.1 voltage regulator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 9.7.2 usb transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 9.7.2.1 output driver characteristics . . . . . . . . . . . . . . . . . . . . . 134 9.7.2.2 low speed (1.5 mbps) driver characteristics . . . . . . . . 134 9.7.2.3 receiver data jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 9.7.2.4 data source jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 9.7.2.5 data signal rise and fall time . . . . . . . . . . . . . . . . . . . 136 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . universal serial bus module (usb) technical data mc68hc908jb8mc68h c08jb8mc68HC08JT8 ? rev. 2.1 118 universal serial bus module (usb) motorola 9.7.3 usb control logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 9.8 i/o registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 9.8.1 usb address register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 9.8.2 usb interrupt register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . 139 9.8.3 usb interrupt register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . 141 9.8.4 usb interrupt register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . 144 9.8.5 usb control register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 9.8.6 usb control register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 9.8.7 usb control register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 9.8.8 usb control register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 9.8.9 usb control register 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 9.8.10 usb status register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 9.8.11 usb status register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 9.8.12 usb endpoint 0 data r egisters . . . . . . . . . . . . . . . . . . . . . 154 9.8.13 usb endpoint 1 data r egisters . . . . . . . . . . . . . . . . . . . . . 155 9.8.14 usb endpoint 2 data r egisters . . . . . . . . . . . . . . . . . . . . . 156 9.9 usb interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 9.9.1 usb end-of-transaction interrupt . . . . . . . . . . . . . . . . . . . 157 9.9.1.1 receive control endpoi nt 0 . . . . . . . . . . . . . . . . . . . . . . 158 9.9.1.2 transmit control e ndpoint 0 . . . . . . . . . . . . . . . . . . . . . 160 9.9.1.3 transmit endpoi nt 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 9.9.1.4 transmit endpoi nt 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 9.9.1.5 receive endpoint 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 9.9.2 resume interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 9.9.3 end-of-packet interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 9.2 introduction this section describes the universal serial bus (usb) module. the usb module is designed to serve as a lo w-speed (ls) usb device per the universal serial bus specification rev 1.1. control and interrupt data transfers are supported. endpoint 0 functions as a transmit/receive control endpoint; endpoint 1 functions as interrupt transmit endpoint; endpoint 2 functions as interrupt transmit or receive endpoint. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . universal serial bus module (usb) features mc68hc908jb8mc68hc08jb8mc68HC08JT8 ? rev. 2.1 technical data motorola universal serial bus module (usb) 119 9.3 features features of the us b module include: full universal serial bus spec ification 1.1 low-speed functions 1.5 mbps data rate on-chip 3.3v regulator endpoint 0 with 8-byte transmit buffer and 8-byte receive buffer endpoint 1 with 8-byte transmit buffer endpoint 2 with 8-byte transmit buffer and 8-byte receive buffer usb data control logic: ? control endpoint 0 and in terrupt endpoints 1 and 2 ? packet decoding/generation ? crc generation and checking ? nrzi (non-return-to zero inserted) enc oding/decoding ? bit-stuffing usb reset options: ? internal mcu reset generation ? cpu interrupt request generation suspend and resume operations , with remote wakeup support usb-generated interrupts: ? transaction interrupt driven ? resume interrupt ? end-of-packet interrupt ? usb reset stall, nak, and a ck handshake generation f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . universal serial bus module (usb) technical data mc68hc908jb8mc68h c08jb8mc68HC08JT8 ? rev. 2.1 120 universal serial bus module (usb) motorola 9.4 pin name conventions the usb share two i/o pins with two port e i/o pi ns. the full name of the usb i/o pin is listed in table 9-1 . the generic pin name appear in the text that follows. table 9-1. usb module pin name conventions usb generic pin names: d+ d? full usb pin names: pte3/d+ pte4/d? addr.register name bit 7654321bit 0 $0018 usb interrupt register 2 (uir2) read: 00000000 write: eopfr rstfr txd2fr rxd2fr txd1fr resumfr txd0fr rxd0fr reset:00000000 $0019 usb control register 2 (ucr2) read: t2seq stall2 tx2e rx2e tp2siz3 tp2siz2 tp2siz1 tp2siz0 write: reset:00000000 $001a usb control register 3 (ucr3) read: tx1st 0 ostall0 istall0 0 pullen enable2 enable1 write: tx1str reset:000000*00 * pullen bit is reset by por or lvi reset only. $001b usb control register 4 (ucr4) read: 00000 fusbo fdp fdm write: reset:00000000 $0020 usb endpoint 0 data register 0 (ue0d0) read: ue0r07 ue0r06 ue0r05 ue0r04 ue0r03 ue0r02 ue0r01 ue0r00 write: ue0t07 ue0t06 ue0t05 ue0t 04 ue0t03 ue0t02 ue0t01 ue0t00 reset: unaffected by reset $0021 usb endpoint 0 data register 1 (ue0d1) read: ue0r17 ue0r16 ue0r15 ue0r14 ue0r13 ue0r12 ue0r11 ue0r10 write: ue0t17 ue0t16 ue0t15 ue0t 14 ue0t13 ue0t12 ue0t11 ue0t10 reset: unaffected by reset = unimplemented u = unaffected by reset figure 9-1. usb i/o register summary (sheet 1 of 4) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . universal serial bus module (usb) pin name conventions mc68hc908jb8mc68hc08jb8mc68HC08JT8 ? rev. 2.1 technical data motorola universal serial bus module (usb) 121 $0022 usb endpoint 0 data register 2 (ue0d2) read: ue0r27 ue0r26 ue0r25 ue0r24 ue0r23 ue0r22 ue0r21 ue0r20 write: ue0t27 ue0t26 ue0t25 ue0t 24 ue0t23 ue0t22 ue0t21 ue0t20 reset: unaffected by reset $0023 usb endpoint 0 data register 3 (ue0d3) read: ue0r37 ue0r36 ue0r35 ue0r34 ue0r33 ue0r32 ue0r31 ue0r30 write: ue0t37 ue0t36 ue0t35 ue0t 34 ue0t33 ue0t32 ue0t31 ue0t30 reset: unaffected by reset $0024 usb endpoint 0 data register 4 (ue0d4) read: ue0r47 ue0r46 ue0r45 ue0r44 ue0r43 ue0r42 ue0r41 ue0r40 write: ue0t47 ue0t46 ue0t45 ue0t 44 ue0t43 ue0t42 ue0t41 ue0t40 reset: unaffected by reset $0025 usb endpoint 0 data register 5 (ue0d5) read: ue0r57 ue0r56 ue0r55 ue0r54 ue0r53 ue0r52 ue0r51 ue0r50 write: ue0t57 ue0t56 ue0t55 ue0t 54 ue0t53 ue0t52 ue0t51 ue0t50 reset: unaffected by reset $0026 usb endpoint 0 data register 6 (ue0d6) read: ue0r67 ue0r66 ue0r65 ue0r64 ue0r63 ue0r62 ue0r61 ue0r60 write: ue0t67 ue0t66 ue0t65 ue0t 64 ue0t63 ue0t62 ue0t61 ue0t60 reset: unaffected by reset $0027 usb endpoint 0 data register 7 (ue0d7) read: ue0r77 ue0r76 ue0r75 ue0r74 ue0r73 ue0r72 ue0r71 ue0r70 write: ue0t77 ue0t76 ue0t75 ue0t 74 ue0t73 ue0t72 ue0t71 ue0t70 reset: unaffected by reset $0028 usb endpoint 1 data register 0 (ue1d0) read: write: ue1t07 ue1t06 ue1t05 ue1t 04 ue1t03 ue1t02 ue1t01 ue1t00 reset: unaffected by reset $0029 usb endpoint 1 data register 1 (ue1d1) read: write: ue1t17 ue1t16 ue1t15 ue1t 14 ue1t13 ue1t12 ue1t11 ue1t10 reset: unaffected by reset $002a usb endpoint 1 data register 2 (ue1d2) read: write: ue1t27 ue1t26 ue1t25 ue1t 24 ue1t23 ue1t22 ue1t21 ue1t20 reset: unaffected by reset $002b usb endpoint 1 data register 3 (ue1d3) read: write: ue1t37 ue1t36 ue1t35 ue1t 34 ue1t33 ue1t32 ue1t31 ue1t30 reset: unaffected by reset addr.register name bit 7654321bit 0 = unimplemented u = unaffected by reset figure 9-1. usb i/o register summary (sheet 2 of 4) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . universal serial bus module (usb) technical data mc68hc908jb8mc68h c08jb8mc68HC08JT8 ? rev. 2.1 122 universal serial bus module (usb) motorola $002c usb endpoint 1 data register 4 (ue1d4) read: write: ue1t47 ue1t46 ue1t45 ue1t 44 ue1t43 ue1t42 ue1t41 ue1t40 reset: unaffected by reset $002d usb endpoint 1 data register5 (ue1d5) read: write: ue1t57 ue1t56 ue1t55 ue1t 54 ue1t53 ue1t52 ue1t51 ue1t50 reset: unaffected by reset $002e usb endpoint 1 data register 6 (ue1d6) read: write: ue1t67 ue1t66 ue1t65 ue1t 64 ue1t63 ue1t62 ue1t61 ue1t60 reset: unaffected by reset $002f usb endpoint 1 data register 7 (ue1d7) read: write: ue1t77 ue1t76 ue1t75 ue1t 74 ue1t73 ue1t72 ue1t71 ue1t70 reset: unaffected by reset $0030 usb endpoint 2 data register 0 (ue2d0) read: ue2r07 ue2r06 ue2r05 ue2r04 ue2r03 ue2r02 ue2r01 ue2r00 write: ue2t07 ue2t06 ue2t05 ue2t 04 ue2t03 ue2t02 ue2t01 ue2t00 reset: unaffected by reset $0031 usb endpoint 2 data register 1 (ue2d1) read: ue2r17 ue2r16 ue2r15 ue2r14 ue2r13 ue2r12 ue2r11 ue2r10 write: ue2t17 ue2t16 ue2t15 ue2t 14 ue2t13 ue2t12 ue2t11 ue2t10 reset: unaffected by reset $0032 usb endpoint 2 data register 2 (ue2d2) read: ue2r27 ue2r26 ue2r25 ue2r24 ue2r23 ue2r22 ue2r21 ue2r20 write: ue2t27 ue2t26 ue2t25 ue2t 24 ue2t23 ue2t22 ue2t21 ue2t20 reset: unaffected by reset $0033 usb endpoint 2 data register 3 (ue2d3) read: ue2r37 ue2r36 ue2r35 ue2r34 ue2r33 ue2r32 ue2r31 ue2r30 write: ue2t37 ue2t36 ue2t35 ue2t 34 ue2t33 ue2t32 ue2t31 ue2t30 reset: unaffected by reset $0034 usb endpoint 2 data register 4 (ue2d4) read: ue2r47 ue2r46 ue2r45 ue2r44 ue2r43 ue2r42 ue2r41 ue2r40 write: ue2t47 ue2t46 ue2t45 ue2t 44 ue2t43 ue2t42 ue2t41 ue2t40 reset: unaffected by reset $0035 usb endpoint 2 data register 5 (ue2d5) read: ue2r57 ue2r56 ue2r55 ue2r54 ue2r53 ue2r52 ue2r51 ue2r50 write: ue2t57 ue2t56 ue2t55 ue2t 54 ue2t53 ue2t52 ue2t51 ue2t50 reset: unaffected by reset addr.register name bit 7654321bit 0 = unimplemented u = unaffected by reset figure 9-1. usb i/o register summary (sheet 3 of 4) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . universal serial bus module (usb) pin name conventions mc68hc908jb8mc68hc08jb8mc68HC08JT8 ? rev. 2.1 technical data motorola universal serial bus module (usb) 123 $0036 usb endpoint 2 data register 6 (ue2d6) read: ue2r67 ue2r66 ue2r65 ue2r64 ue2r63 ue2r62 ue2r61 ue2r60 write: ue2t67 ue2t66 ue2t65 ue2t 64 ue2t63 ue2t62 ue2t61 ue2t60 reset: unaffected by reset $0037 usb endpoint 2 data register 7 (ue2d7) read: ue2r77 ue2r76 ue2r75 ue2r74 ue2r73 ue2r72 ue2r71 ue2r70 write: ue2t77 ue2t76 ue2t75 ue2t 74 ue2t73 ue2t72 ue2t71 ue2t70 reset: unaffected by reset $0038 usb address register (uaddr) read: usben uadd6 uadd5 uadd4 uadd3 uadd2 uadd1 uadd0 write: reset:0*0000000 * usben bit is reset by por or lvi reset only. $0039 usb interrupt register 0 (uir0) read: eopie suspnd txd2ie rxd2ie txd1ie 0 txd0ie rxd0ie write: reset:00000000 $003a usb interrupt register 1 (uir1) read: eopf rstf txd2f rxd2f txd1f resumf txd0f rxd0f write: reset:00000000 $003b usb control register 0 (ucr0) read: t0seq 0 tx0e rx0e tp0siz3 tp0siz2 tp0siz1 tp0siz0 write: reset:00000000 $003c usb control register 1 (ucr1) read: t1seq stall1 tx1e fresum tp1siz3 tp1siz2 tp1siz1 tp1siz0 write: reset:00000000 $003d usb status register 0 (usr0) read: r0seq setup 0 0 rp0siz3 rp0siz2 rp0siz1 rp0siz0 write: reset: unaffected by reset $003e usb status register 1 (usr1) read: r2seq txack txnak txstl rp2siz3 rp2siz2 rp2siz1 rp2siz0 write: reset:u0 0 0uuuu addr.register name bit 7654321bit 0 = unimplemented u = unaffected by reset figure 9-1. usb i/o register summary (sheet 4 of 4) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . universal serial bus module (usb) technical data mc68hc908jb8mc68h c08jb8mc68HC08JT8 ? rev. 2.1 124 universal serial bus module (usb) motorola 9.5 functional description figure 9-2 shows the block diagram of the usb m odule. the usb module manages communications be tween the host and the usb function. the module is partitioned into three functional blocks. these blocks consist of a dual-function tran sceiver, the usb control logic, and the endpoint registers. the blocks are further detailed later in this section (see 9.7 hardware description ). figure 9-2. usb block diagram d + d ? transceiver rcv vpin vmin vpout vmout cpu bus usb registers usb upstream port usb control logic f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . universal serial bus module (usb) functional description mc68hc908jb8mc68hc08jb8mc68HC08JT8 ? rev. 2.1 technical data motorola universal serial bus module (usb) 125 9.5.1 usb protocol figure 9-3 shows the various transaction types s upported by the usb module. the transactions ar e portrayed as error free. the effect of errors in the data flow are discussed later. figure 9-3. supported tr ansaction types per endpoint setup in out data0/1 data0 data1 ack data1 out ack out data0 ack ack data0/1 endpoint 0 transactions: control write control read no-data control endpoints 1 & 2 transactions: interrupt bulk transmit in ack key: unrelated bus traffic host generated device generated ack setup out in data0/1 data0 data1 ack data1 in ack in data0 ack ack ack setup in data0 data1 ack ack data0/1 in ack f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . universal serial bus module (usb) technical data mc68hc908jb8mc68h c08jb8mc68HC08JT8 ? rev. 2.1 126 universal serial bus module (usb) motorola each usb transaction is comprised of a series of pa ckets. the usb module supports the packet types shown in figure 9-4 . token packets are generated by the usb host and dec oded by the usb device. data and handshake packets are both dec oded and generat ed by the usb device, depending on the type of transaction. figure 9-4. suppor ted usb packet types the following sections detail each segm ent used to form a complete usb transaction. 9.5.1.1 sync pattern the nrzi bit pattern shown in figure 9-5 is used as a synchronization pattern and is prefixed to each packet. this pattern is equivalent to a data pattern of seven 0s followed by a 1 ($80). figure 9-5. sync pattern token packet: in out sync pid pid addr endp crc5 eop setup data packet: data0 sync pid pid data crc16 eop data1 0 ? 8 bytes handshake packet: ack nak sync pid pid eop stall sync pattern pid0 pid1 idle nrzi data encoding f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . universal serial bus module (usb) functional description mc68hc908jb8mc68hc08jb8mc68HC08JT8 ? rev. 2.1 technical data motorola universal serial bus module (usb) 127 the start of a packet (sop ) is signaled by the orig inating port by driving the d+ and d? lines from the idle state (also referred to as the j state) to the opposite logi c level (also referred to as the k state). this switch in levels represents the firs t bit of the sync field. figure 9-6 shows the data signaling and voltage leve ls for the start of pa cket and the sync pattern. figure 9-6. sop, sync si gnaling, and voltage levels 9.5.1.2 packet identifier field the packet identifier field is an 8- bit number comprised of the 4-bit packet identification and its comple ment. the field follows the sync pattern and determines the direction and type of transaction on the bus. table 9-2 shows the packet identifier va lues for the supported packet types. end of sync first bit of packet sop bus idle v oh (min.) v se (max) v se (min.) v ol (min.) v ss table 9-2. supported packet identifiers packet identifier value packet identifier type %1001 in token %0001 out token %1101 setup token %0011 data0 packet %1011 data1 packet %0010 ack handshake %1010 nak handshake %1110 stall handshake f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . universal serial bus module (usb) technical data mc68hc908jb8mc68h c08jb8mc68HC08JT8 ? rev. 2.1 128 universal serial bus module (usb) motorola 9.5.1.3 address field (addr) the address field is a 7-bit number that is used to select a particular usb device. this field is compared to the lower seven bi ts of the uaddr register to deter mine if a given transaction is targeting the mcu usb device. 9.5.1.4 endpoint field (endp) the endpoint field is a 4-bit number th at is used to select a particular endpoint within a usb devic e. for the mcu, this will be a binary number between 0 and 2 inclusive. any other value will cause the transaction to be ignored. 9.5.1.5 cyclic redundancy check (crc) cyclic redundancy checks are used to verify the address and data stream of a usb transacti on. this field is five bi ts wide for token packets and 16 bits wide for data packets. crcs are generated in the transmitter and sent on the usb data lines after both the endpoint fi eld and the data field. 9.5.1.6 end-of-packet (eop) the single-ended 0 (se0) state is us ed to signal an end-of-packet (eop). the single- ended 0 state is indicated by both d+ and d? being below 0.8v. eop will be signaled by driv ing d+ and d? to the single-ended 0 state for two bit times followed by dr iving the lines to the idle state for one bit time. the transition from the single-ended 0 to the idle state defines the e nd of the packet. the idle state is asserted for one bit time and then both the d+ and d? output drivers ar e placed in their high-impedance state. the bus termination resistor s hold the bus in the idle state. figure 9-7 shows the data signaling and voltage levels for an end-of-packet transaction. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . universal serial bus module (usb) functional description mc68hc908jb8mc68hc08jb8mc68HC08JT8 ? rev. 2.1 technical data motorola universal serial bus module (usb) 129 figure 9-7. eop transaction voltage levels the width of the se0 in the eop is about two bit times. the eop width is measured with the same capacitive load used for maximum rise and fall times and is measured at the same level as the differential signal crossover points of the data lines. figure 9-8. eop width timing 9.5.2 reset signaling the usb module will de tect a reset signaled on t he bus by the presence of an extended se0 at t he usb data pins of a device. the mcu seeing a single-ended 0 on its usb data inputs for more than 8 s treats that signal as a reset. a usb sourced reset will hold the mcu in reset fo r the duration of the reset on the usb bus. the usb bit in the reset status register (rsr) will be set after the internal reset is removed. refer to 8.8.2 reset status register for more detail. the mcu?s reset recovery sequence is detailed in section 8. system in tegration module (sim) . bus driven to last bit of bus idle eop strobe packet idle state bus floats v oh (min.) v se (max) v se (min.) v ol (min.) v ss eop width t period differential data lines data crossover level f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . universal serial bus module (usb) technical data mc68hc908jb8mc68h c08jb8mc68HC08JT8 ? rev. 2.1 130 universal serial bus module (usb) motorola the reset flag bit (rst f) in the usb interrupt regi ster 1 (uir1) also will be set after the internal re set is removed. refer to 9.8.3 usb interrupt register 1 for more detail. after a reset is removed, the device will be in the def ault, but not yet addressed or configured state (refer to section 9.1 usb device states of the universal serial bus specification rev. 1.1). the device must be able to accept a device address via a set_address command (refer to section 9.4 standard device request in the universal serial bus specification rev. 1.1) no later than 10 ms after the reset is removed. reset can wake a device from the suspended mode. note: usb reset can be configured not to gen erate a reset signal to the cpu by setting the urstd bit of the confi guration register (see section 5. configuration register (config) ) . when a usb reset is detected, the cpu generates an usb interrupt. 9.5.3 suspend the mcu supports suspend mode for low power. sus pend mode should be entered when the usb data lines are in the idle state for more than 3ms. entry into suspen d mode is controlled by the suspnd bit in the usb interrupt register . any low-speed bus ac tivity should keep the device out of the suspend state. low-speed device s are kept awake by periodic low-speed eop signals from the host. this is referred to as low speed keep alive (refer to section 11. 8.4.1 low-speed keep-alive in the universal serial bus specification rev. 1.1). firmware should monitor the eo pf flag and enter suspend mode by setting the suspnd bi t if an eop is not detected for 3ms. per the usb specificati on, the bus powered usb system is required to draw less than 500 a from the v dd supply when in th e suspend state. this includes the current supplied by the voltage regulator to the 1.5k ? to ground termination resi stors placed at the ho st end of the usb bus. this low-current requirement means that fi rmware is responsible for entering stop mode once the usb module has been placed in the suspend state. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . universal serial bus module (usb) functional description mc68hc908jb8mc68hc08jb8mc68HC08JT8 ? rev. 2.1 technical data motorola universal serial bus module (usb) 131 9.5.4 resume after suspend the mcu can be activated from t he suspend state by normal bus activity, a usb reset signal, or by a forced resume dr iven from the mcu. 9.5.4.1 host initiated resume the host signals resume by initiating resume signallin g (k state) for at least 20ms followed by a stan dard low-speed eop signal. this 20ms ensures that all devices in the usb network are awakened. after resuming the bus, the host mu st begin sending bus traffic within 37ms to prevent the device from re-entering suspend mode. 9.5.4.2 usb reset signalling reset can wake a device from the suspended mode. 9.5.4.3 remote wakeup the mcu also supports the remote wakeup feature. the firmware has the ability to exit su spend mode by signaling a resume state to the upstream host or hub. a non-idle state (k state) on the usb data lines is accomplished by asserting the fr esum bit in the ucr1 register. when using the remote wakeup capability , the firmware must wait for at least 5ms after the bus is in the id le state before se nding the remote wakeup resume signaling. this allows the upstream devices to get into their suspend state and prepare for propagating resume signaling. the fresum bit should be asserted to cause the resume state on the usb data lines for at least 10ms, but not more than 15ms. note that the resume signalling is controlled by the fre sum bit and meeting the timing specifications is dependent on the firmware. when fresum is cleared by firmware, the da ta lines will return to their high-impedance state. refer to the register definitions (see 9.8.6 usb contro l register 1 ) for more information about how the force resume (fresum) bit can be used to initiate the remote wakeup feature. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . universal serial bus module (usb) technical data mc68hc908jb8mc68h c08jb8mc68HC08JT8 ? rev. 2.1 132 universal serial bus module (usb) motorola 9.5.5 low-speed device low-speed devices are conf igured by the position of a pull-up resistor on the usb d? pin of t he mcu. low-speed device s are terminated as shown in figure 9-9 with the pull- up on the d? line. figure 9-9. external low-s peed device c onfiguration for low-speed transmissions, the tr ansmitter?s eop width must be between 1.25 s and 1.50 s. these ranges include ti ming variations due to differential buffer del ay and rise/fall time mismatches and to noise and other random effects. a low-speed re ceiver must accept a 670ns se0 followed by a j transition as a valid eop. an se0 shorter than 330ns or an se0 not followed by a j transition are rejected as an eop. any se0 that is 8 s or longer is automatically a reset. 9.6 clock requirements the low-speed data rate is nomi nally 1.5 mbps. the oscxclk signal driven by the oscillator circuits is the clock source for the usb module and requires that a 6-mh z oscillator circuit be connected to the osc1 and osc2 pins. the permitted fr equency tolerance for low-speed functions is approximately 1.5% (15,000 ppm). this tolerance includes inaccuracies from all sources: initial frequency ac curacy, crystal capacitive loading, supply voltage on the oscillator, temperature, and aging. the jitter in the low-speed data rate mu st be less than 10ns. 1.5 k ? d+ d? v reg (3.3v) usb low-speed cable mcu f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . universal serial bus module (usb) hardware description mc68hc908jb8mc68hc08jb8mc68HC08JT8 ? rev. 2.1 technical data motorola universal serial bus module (usb) 133 9.7 hardware description the usb module as prev iously shown in figure 9-2 contains three functional blocks: the lo w-speed usb transceiver, the usb control logic, and the usb registers. the following details the f unction of the regulator, transceiver, and cont rol logic. see 9.8 i/o registers for details of register settings. 9.7.1 voltage regulator the usb data lines are required by the usb specific ation to have an output voltage between 2.8v and 3.6v. the data lin es also are required to have an external 1.5k ? pull-up resistor connec ted between a data line and a voltage source between 3.0v and 3.6v. figure 9-10 shows the worst case electrical connecti on for the vo ltage regulator. figure 9-10. regulator electrical connections 9.7.2 usb transceiver the usb transceiver provides the physi cal interface to the usb d+ and d? data lines. the transceiver is composed of two parts: an output drive circuit and a receiver. r1 d+ d? usb cable low-speed transceiver r2 r2 host or hub 3.3v regulator 4.0v ? 5.5v usb data lines r1 = 1.5k ? 5% r2 = 15k ? 5% f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . universal serial bus module (usb) technical data mc68hc908jb8mc68h c08jb8mc68HC08JT8 ? rev. 2.1 134 universal serial bus module (usb) motorola 9.7.2.1 output driv er characteristics the usb transceiver uses a differentia l output driver to drive the usb data signal onto the usb c able. the static output sw ing of the driver in its low state is below the v ol of 0.3v with a 1.5k ? load to 3.6v and in its high state is above the v oh of 2.8v with a 15k ? load to ground. the output swings between th e differential high an d low state are well balanced to minimize signal skew. slew rate control on the driver is used to minimize the radi ated noise and cross talk . the driver?s outputs support 3-state operation to achieve bidirectional ha lf duplex operation. the driver can tolerate a voltage on t he signal pins of ?1 .0v to 5.5v with respect to local ground reference without damage. 9.7.2.2 low speed (1.5 mbps) driver characteristics the rise and fall time of the signals on this cable are gr eater than 75ns and less than 300ns. the ed ges are matched to within 20% to minimize rfi emissions and signal skew. usb data transmission is done with di fferential signals. a differential input receiver is used to accept the usb data signal. a differential 1 on the bus is represented by d+ being at least 200mv more positive than d? as seen at the receiver, and a differential 0 is represented by d? being at least 200mv more positive t han d+ as seen at the receiver. the signal cross over point must be between 1.3v and 2.0v. figure 9-11. recei ver characteristics one bit time (1.5 mb/s) signal pins pass output spec levels with minimal reflections and ringing v se (min.) v se (max) v ss f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . universal serial bus module (usb) hardware description mc68hc908jb8mc68hc08jb8mc68HC08JT8 ? rev. 2.1 technical data motorola universal serial bus module (usb) 135 the receiver features an input sensitivity of 200mv when both differential data inputs are in the differential comm on mode range of 0.8v to 2.5v as shown in figure 9-12 . in addition to the differential receiver, there is a singl e-ended receiver (sch mitt trigger) fo r each of the two data lines. figure 9-12. differential input sensitivity range 9.7.2.3 receiver data jitter the data receivers for all types of devices must be able to properly decode the differential data in the pres ence of jitter. the more of the bit time that any data edge can occupy and still be decoded, the more reliable the data transfer will be. data receivers are required to decode differential data transiti ons that occur in a window plus and minus a nominal quarter bit time from the nominal (center ed) data edge position. jitter will be caused by the delay mi smatches and by mismatches in the source and destination data rates (frequencies). the receive data jitter budget for low speed is given in section 18. electri cal specifications . the specification include s the consecutive (nex t) and paired transition values for each source of jitter. 9.7.2.4 data source jitter the source of data can have some variat ion (jitter) in t he timing of edges of the data transmitted. the time between any set of data transitions is n t period jitter time, where n is the number of bits between the transitions and t period is defined as the actual period of the data rate. the data jitter is measured with th e same capacitive load used for maximum rise and fall time s and is measured at t he crossover points of the data lines as shown in figure 9-13 . differential output crossover voltage range differential input voltage range input voltage range (volts) 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 ?1.0 5.5 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . universal serial bus module (usb) technical data mc68hc908jb8mc68h c08jb8mc68HC08JT8 ? rev. 2.1 136 universal serial bus module (usb) motorola figure 9-13. data jitter for low-speed transmissions, the ji tter time for any consecutive differential data transiti ons must be within 25ns and within 10ns for any set of paired diff erential data transitions. these jitter numbers include timing variati ons due to differential buff er delay, rise/fall time mismatches, internal clock source ji tter, noise and ot her random effects. 9.7.2.5 data signal rise and fall time the output rise time and fall time are measured between 10% and 90% of the signal. edge tran sition time for the risi ng and falling edges of low-speed signals is 75ns (minimu m) into a capacitive load (c l ) of 200pf and 300ns (maximum) into a c apacitive load of 600pf. the rising and falling edges should be transitioni ng (monotonic) smoothly when driving the cable to avoid excessive emi. figure 9-14. data si gnal rise and fall time consecutive transitions t period differential data lines crossover points paired transitions jitter t r differential data lines t f rise time fall time 10% 90% 90% 10% low speed: 75ns at c l = 200pf, 300ns at c l = 600 pf c l c l + + f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . universal serial bus module (usb) i/o registers mc68hc908jb8mc68hc08jb8mc68HC08JT8 ? rev. 2.1 technical data motorola universal serial bus module (usb) 137 9.7.3 usb control logic the usb control logic m anages data movement between the cpu and the transceiver. the control logic handles both transmit and receive operations on the usb. it contains the logic used to manipulate the transceiver and the endpoint registers. the byte count buffer is loaded with the active transmit endpoints byte count value during trans mit operations. this same buffer is used for receive transactions to count th e number of bytes received and, upon the end of the transaction, transfer that number to the receive endpoints byte count register. when transmitting, the control logic handles parallel-to-serial conversion, crc generation, nrzi encoding, and bit stuffing. when receiving, the control logi c handles sync detection, packet identification, end-of-pa cket detection, bi t (un)stuffing, nrzi decoding, crc validation, and serial -to-parallel conversion. errors detected by the control logic include bad crc, timeou t while waiting for eop, and bit stuffing violations. 9.8 i/o registers these i/o registers control and monitor usb operation: usb address r egister (uaddr) usb control regi sters 0?4 (ucr0?ucr4) usb status registers 0?1 (usr0?usr1) usb interrupt regi sters 0?2 (uir0?uir2) usb endpoint 0 data regi sters 0?7 (ue0d0?ue0d7) usb endpoint 1 data regi sters 0?7 (ue1d0?ue1d7) usb endpoint 2 data regi sters 0?7 (ue2d0?ue2d7) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . universal serial bus module (usb) technical data mc68hc908jb8mc68h c08jb8mc68HC08JT8 ? rev. 2.1 138 universal serial bus module (usb) motorola 9.8.1 usb address register usben ? usb module enable this read/write bit enables and dis ables the usb mo dule and the usb pins. when usben is set, the usb module is enabled and the pte4 interrupt is disabled. when usben is clear, t he usb module will not respond to any tokens, usb reset and usb related interrupts are disabled, and pins pte4/d? and pte3/d+ function as high current open-drain i/o port pins pte4 and pte3. 1 = usb function enabled and pte4 interrupt is disabled 0 = usb function disabled includ ing usb interrupt, reset and reset interrupt uadd[6:0] ? usb function address these bits specify the usb address of the device. reset clears these bits. address: $0038 bit 7654321bit 0 read: usben uadd6 uadd5 uadd4 uadd3 uadd2 uadd1 uadd0 write: reset: 0*0000000 * usben bit is reset by por or lvi reset only. figure 9-15. usb addr ess register (uaddr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . universal serial bus module (usb) i/o registers mc68hc908jb8mc68hc08jb8mc68HC08JT8 ? rev. 2.1 technical data motorola universal serial bus module (usb) 139 9.8.2 usb interrupt register 0 eopie ? end-of-packet de tect interrupt enable this read/write bit enabl es the usb to gener ate cpu interrupt requests when the eopf bit become s set. reset clears the eopie bit. 1 = end-of-packet sequence detection can generate a cpu interrupt request 0 = end-of-packet sequence detection cannot generate a cpu interrupt request suspnd ? usb suspend bit to save power, this read/write bit should be set by the software if a 3ms constant idle stat e is detected on the us b bus. setting this bit puts the transceiver into a po wer-saving mode. the resumf flag must be cleared before se tting suspnd. software must clear this bit after the resume flag (resumf) is set while this resume interrupt flag is serviced. txd2ie ? endpoint 2 tr ansmit interrupt enable this read/write bit enabl es the transmit endpoi nt 2 to generate cpu interrupt requests when the txd2f bi t becomes set. reset clears the txd2ie bit. 1 = transmit endpoint 2 can gener ate a cpu interrupt request 0 = transmit endpoint 2 cannot generate a cp u interrupt request address: $0039 bit 7654321bit 0 read: eopie suspnd txd2ie rxd2ie txd1ie 0 txd0ie rxd0ie write: reset:00000000 = unimplemented figure 9-16. usb interrupt register 0 (uir0) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . universal serial bus module (usb) technical data mc68hc908jb8mc68h c08jb8mc68HC08JT8 ? rev. 2.1 140 universal serial bus module (usb) motorola rxd2ie ? endpoint 2 re ceive interrupt enable this read/write bit enabl es the receive endpoint 2 to gen erate cpu interrupt requests when the rxd2f bi t becomes set. reset clears the rxd2ie bit. 1 = receive endpoint 2 can gener ate a cpu interrupt request 0 = receive endpoint 2 cannot ge nerate a cpu interrupt request txd1ie ? endpoint 1 tr ansmit interrupt enable this read/write bit enabl es the transmit endpoi nt 1 to generate cpu interrupt requests when the txd1f bi t becomes set. reset clears the txd1ie bit. 1 = transmit endpoints 1 can gener ate a cpu inte rrupt request 0 = transmit endpoints 1 cannot gen erate a cpu interrupt request txd0ie ? endpoint 0 tr ansmit interrupt enable this read/write bit enabl es the transmit endpoi nt 0 to generate cpu interrupt requests when the txd0f bi t becomes set. reset clears the txd0ie bit. 1 = transmit endpoint 0 can gener ate a cpu interrupt request 0 = transmit endpoint 0 cannot generate a cp u interrupt request rxd0ie ? endpoint 0 re ceive interrupt enable this read/write bit enabl es the receive endpoint 0 to gen erate cpu interrupt requests when the rxd0f bi t becomes set. reset clears the rxd0ie bit. 1 = receive endpoint 0 can gener ate a cpu interrupt request 0 = receive endpoint 0 cannot ge nerate a cpu interrupt request f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . universal serial bus module (usb) i/o registers mc68hc908jb8mc68hc08jb8mc68HC08JT8 ? rev. 2.1 technical data motorola universal serial bus module (usb) 141 9.8.3 usb interrupt register 1 eopf ? end-of-packet detect flag this read-only bit is set when a va lid end-of-packe t sequence is detected on the d+ and d? lines. software must clear this flag by writing a logic 1 to the eopfr bit. reset clears this bit. writi ng to eopf has no effect. 1 = end-of-packet sequen ce has been detected 0 = end-of-packet sequence has not been detected rstf ? usb reset flag this read-only bit is set when a valid reset signal state is detected on the d+ and d? lines. if the urstd bit of the configuration register (config) is clear, this reset detec tion will generate an internal reset signal to reset the cpu and other periphera ls including the usb module. if the urstd bit is set, th is reset detection will generate an usb interrupt. this bit is cleared by writing a logic 1 to the rstfr bit. this bit also is cleared by a por reset. note: the usb bit in the rsr register (see 8.8.2 reset st atus register ) is also a usb reset indicator. txd2f ? endpoint 2 data transmit flag this read-only bit is set after the data stored in endpoint 2 transmit buffers has been sent and an ack handshake packet from the host is received. once the next set of data is ready in the transmit buffers, software must clear this flag by wr iting a logic 1 to the txd2fr bit. address: $003a bit 7654321bit 0 read: eopf rstf txd2f rxd2f txd1f resumf txd0f rxd0f write: reset:00000000 = unimplemented figure 9-17. usb interrupt register 1 (uir1) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . universal serial bus module (usb) technical data mc68hc908jb8mc68h c08jb8mc68HC08JT8 ? rev. 2.1 142 universal serial bus module (usb) motorola to enable the next data packet transmissi on, tx2e also must be set. if the txd2f bit is not cleared, a nak handshak e will be returned in the next in transaction. reset clears this bit. writi ng to txd2f has no effect. 1 = transmit on endpoint 2 has occurred 0 = transmit on endpoint 2 has not occurred rxd2f ? endpoint 2 data receive flag this read-only bit is set after t he usb module has received a data packet and responded with an a ck handshake packet. software must clear this flag by writing a logic 1 to the rxd2fr bit after all of the received data has been read. software also mu st set the rx2e bit to 1 to enable the next data packet rec eption. if the rx d2f bit is not cleared, a nak handshake will be returned in the next out transaction. reset clears this bit. writi ng to rxd2f has no effect. 1 = receive on endpoint 2 has occurred 0 = receive on endpoint 2 has not occurred txd1f ? endpoint 1 data transmit flag this read-only bit is set after the dat a stored in the e ndpoint 1 transmit buffer has been sent and an ack handshake packet from the host is received. once the next set of data is ready in the transmit buffers, software must clear this flag by writ ing a logic 1 to t he txd1fr bit. to enable the next data packet transmissi on, tx1e also must be set. if the txd1f bit is not cl eared, a nak handshake wi ll be returned in the next in transaction. reset clears this bit. writi ng to txd1f has no effect. 1 = transmit on endpoi nt 1has occurred 0 = transmit on endpoint 1has not occurred resumf ? resume flag this read-only bit is set when usb bu s activity is detected while the suspnd bit is set. software must clear this flag by wr iting a logic 1 to the resumfr bit. reset clears this bit. writing a lo gic 0 to resumf has no effect. 1 = usb bus activity has been detected 0 = no usb bus activity has been detected f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . universal serial bus module (usb) i/o registers mc68hc908jb8mc68hc08jb8mc68HC08JT8 ? rev. 2.1 technical data motorola universal serial bus module (usb) 143 txd0f ? endpoint 0 data transmit flag this read-only bit is set after the data stored in endpoint 0 transmit buffers has been sent and an ack handshake packet from the host is received. once the next set of data is ready in the transmit buffers, software must clear this flag by writ ing a logic 1 to t he txd0fr bit. to enable the next data packet transmissi on, tx0e also must be set. if the txd0f bit is not cl eared, a nak handshake wi ll be returned in the next in transaction. reset clears this bit. writi ng to txd0f has no effect. 1 = transmit on endpoint 0 has occurred 0 = transmit on endpoint 0 has not occurred rxd0f ? endpoint 0 data receive flag this read-only bit is set after t he usb module has received a data packet and responded with an a ck handshake packet. software must clear this flag by writing a logic 1 to the rxd0fr bit after all of the received data has been read. software also mu st set the rx0e bit to 1 to enable the next data packet rec eption. if the rx d0f bit is not cleared, the usb will respon d with a nak handshake to any endpoint 0 out tokens; but does not respond to a setup token. reset clears this bit. writi ng to rxd0f has no effect. 1 = receive on endpoint 0 has occurred 0 = receive on endpoint 0 has not occurred f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . universal serial bus module (usb) technical data mc68hc908jb8mc68h c08jb8mc68HC08JT8 ? rev. 2.1 144 universal serial bus module (usb) motorola 9.8.4 usb interrupt register 2 eopfr ? end-of-p acket flag reset writing a logic 1 to this write-only bit w ill clear the eopf bit if it is set. writing a logic 0 to the eopfr ha s no effect. reset clears this bit. rstfr ? clear reset indicator bit writing a logic 1 to this write-only bit will clear t he rstf bit if it is set. writing a logic 0 to the rstfr has no effect. reset clears this bit. txd2fr ? endpoint 2 transmit flag reset writing a logic 1 to this wr ite-only bit will clear the txd2f bit if it is set. writing a logic 0 to t xd2fr has no effect. reset clears this bit. rxd2fr ? endpoint 2 receive flag reset writing a logic 1 to this write-only bit will clear the rxd2f bit if it is set. writing a logic 0 to rxd2fr has no effect. reset clears this bit. txd1fr ? endpoint 1 transmit flag reset writing a logic 1 to this wr ite-only bit will clear the txd1f bit if it is set. writing a logic 0 to t xd1fr has no effect. reset clears this bit. resumfr ? resume flag reset writing a logic 1 to this write-only bit will clear the resumf bit if it is set. writing to resumfr has no effect. reset clears this bit. txd0fr ? endpoint 0 transmit flag reset writing a logic 1 to this wr ite-only bit will clear the txd0f bit if it is set. writing a logic 0 to t xd0fr has no effect. reset clears this bit. rxd0fr ? endpoint 0 receive flag reset writing a logic 1 to this write-only bit will clear the rxd0f bit if it is set. writing a logic 0 to rxd0fr has no effect. reset clears this bit. address: $0018 bit 7654321bit 0 read: 00 0 0 0 0 0 0 write: eopfr rstfr txd2fr rxd2fr txd1fr resumfr txd0fr rxd0fr reset:00000000 figure 9-18. usb interrupt register 2 (uir2) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . universal serial bus module (usb) i/o registers mc68hc908jb8mc68hc08jb8mc68HC08JT8 ? rev. 2.1 technical data motorola universal serial bus module (usb) 145 9.8.5 usb control register 0 t0seq ? endpoint 0 tr ansmit sequence bit this read/write bit deter mines which type of da ta packet (data0 or data1) will be sent during the next in tr ansaction directed at endpoint 0. toggling of this bit must be controlled by software. reset clears this bit. 1 = data1 token active fo r next endpoint 0 transmit 0 = data0 token active fo r next endpoint 0 transmit tx0e ? endpoint 0 transmit enable this read/write bi t enables a transmit to occur when the usb host controller sends an in token to e ndpoint 0. software should set this bit when data is ready to be transmi tted. it must be cleared by software when no more endpoint 0 data needs to be transmitted. if this bit is 0 or the txd0f is set, the usb will re spond with a nak handshake to any endpoint 0 in tokens. reset cl ears this bit. 1 = data is ready to be sent 0 = data is not ready. respond with nak rx0e ? endpoint 0 receive enable this read/write bit enabl es a receive to occur when the usb host controller sends an out token to endpoint 0. software should set this bit when data is ready to be received. it must be cleared by software when data cannot be received. if this bit is 0 or the rxd0f is set, the usb wil l respond with a nak handshake to any endpoint 0 out to kens; but does not respond to a setup token. rese t clears this bit. 1 = data is ready to be received 0 = not ready for data. respond with nak address: $003b bit 7654321bit 0 read: t0seq 0 tx0e rx0e tp0siz3 tp0siz2 tp0siz1 tp0siz0 write: reset:00000000 figure 9-19. u sb control register 0 (ucr0) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . universal serial bus module (usb) technical data mc68hc908jb8mc68h c08jb8mc68HC08JT8 ? rev. 2.1 146 universal serial bus module (usb) motorola tp0siz3?tp0siz0 ? endpoint 0 transmit data packet size these read/write bits st ore the number of trans mit data bytes for the next in token request for endpoint 0. these bits are cleared by reset. 9.8.6 usb control register 1 t1seq ? endpoint 1 tr ansmit sequence bit this read/write bit deter mines which type of da ta packet (data0 or data1) will be sent during the next in tr ansaction directed to endpoint 1. toggling of this bit must be controlled by software. reset clears this bit. 1 = data1 token active fo r next endpoint 1 transmit 0 = data0 token active fo r next endpoint 1 transmit stall1 ? endpoint 1 force stall bit this read/write bit caus es endpoint 1 to retu rn a stall handshake when polled by either an in or ou t token by the usb host controller. reset clears this bit. 1 = send stall handshake 0 = default tx1e ? endpoint 1 transmit enable this read/write bi t enables a transmit to occur when the usb host controller sends an in token to endpoint 1. the appropriate endpoint enable bit, enable1 bit in the ucr3 register , also should be set. software should set the tx1e bit when data is ready to be transmitted. it must be cleared by software when no more data needs to be transmitted. address: $003c bit 7654321bit 0 read: t1seq stall1 tx1e fresum tp1siz3 tp1siz2 tp1siz1 tp1siz0 write: reset:00000000 figure 9-20. u sb control register 1 (ucr1) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . universal serial bus module (usb) i/o registers mc68hc908jb8mc68hc08jb8mc68HC08JT8 ? rev. 2.1 technical data motorola universal serial bus module (usb) 147 if this bit is 0 or the txd1f is set, the usb will re spond with a nak handshake to any endpoint 1 directed in tokens. reset clears this bit. 1 = data is ready to be sent 0 = data is not ready. respond with nak fresum ? force resume this read/write bit forces a resume st ate (k or non-idle state) onto the usb data lines to init iate a remote wakeup. software should control the timing of the forc ed resume to be between 10 and 15 ms. setting this bit will not cause the resumf bit to be set. 1 = force data lines to k state 0 = default tp1siz3?tp1siz0 ? endpoint 1 transmit data packet size these read/write bits st ore the number of trans mit data bytes for the next in token request for endpoint 1. these bits are cleared by reset. 9.8.7 usb control register 2 t2seq ? endpoint 2 tr ansmit sequence bit this read/write bit deter mines which type of da ta packet (data0 or data1) will be sent during the next in tr ansaction directed to endpoint 2. toggling of this bit must be controlled by software. reset clears this bit. 1 = data1 token active fo r next endpoint 2 transmit 0 = data0 token active fo r next endpoint 2 transmit address: $0019 bit 7654321bit 0 read: t2seq stall2 tx2e rx2e tp2siz3 tp2siz2 tp2siz1 tp2siz0 write: reset:00000000 figure 9-21. u sb control register 2 (ucr2) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . universal serial bus module (usb) technical data mc68hc908jb8mc68h c08jb8mc68HC08JT8 ? rev. 2.1 148 universal serial bus module (usb) motorola stall2 ? endpoint 2 force stall bit this read/write bit caus es endpoint 2 to retu rn a stall handshake when polled by either an in or ou t token by the usb host controller. reset clears this bit. 1 = send stall handshake 0 = default tx2e ? endpoint 2 transmit enable this read/write bi t enables a transmit to occur when the usb host controller sends an in token to endpoint 2. the appropriate endpoint enable bit, enable2 bit in the ucr3 register , also should be set. software should set the tx2e bit when data is ready to be transmitted. it must be cleared by software when no more data needs to be transmitted. if this bit is 0 or the txd2f is set, the usb will re spond with a nak handshake to any endpoint 2 directed in tokens. reset clears this bit. 1 = data is ready to be sent 0 = data is not ready. respond with nak rx2e ? endpoint 2 receive enable this read/write bit enabl es a receive to occur when the usb host controller sends an out token to endpoint 2. software should set this bit when data is ready to be received. it must be cleared by software when data cannot be received. if this bit is 0 or the rxd2f is set, the usb wil l respond with a nak handshake to any endpoint 2 out tokens. reset clears this bit. 1 = data is ready to be received 0 = not ready for data. respond with nak tp2siz3?tp2siz0 ? endpoint 2 transmit data packet size these read/write bits st ore the number of trans mit data bytes for the next in token request for endpoint 2. these bits are cleared by reset. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . universal serial bus module (usb) i/o registers mc68hc908jb8mc68hc08jb8mc68HC08JT8 ? rev. 2.1 technical data motorola universal serial bus module (usb) 149 9.8.8 usb control register 3 tx1st ? endpoint 0 transmit first flag this read-only bit is set if the endpoint 0 data transmit flag (txd0f) is set when the usb control logic is setting the endpoint 0 data receive flag (rxd0f). in other words, if an unserviced endpoint 0 transmit flag is still set at the end of an endpoint 0 recepti on, then this bi t will be set. this bit lets the firmware know that th e endpoint 0 transmission happened before the endpoi nt 0 reception. reset clears this bit. 1 = in transaction occu rred before setup/out 0 = in transaction occu rred after setup/out tx1str ? clear endpoint 0 transmit first flag writing a logic 1 to this write-only bit will cl ear the tx1st bit if it is set. writing a logic 0 to t he tx1str has no effect. reset clears this bit. ostall0 ? endpoint 0 force stall bit for out token this read/write bit caus es endpoint 0 to retu rn a stall handshake when polled by an out token by the usb host controller. reset clears this bit. 1 = send stall handshake 0 = default address: $001a bit 7654321bit 0 read: tx1st 0 ostall0 istall0 0 pullen enable2 enable1 write: tx1str reset:000000*00 = unimplemented * pullen bit is reset by por or lvi reset only. figure 9-22. u sb control register 3 (ucr3) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . universal serial bus module (usb) technical data mc68hc908jb8mc68h c08jb8mc68HC08JT8 ? rev. 2.1 150 universal serial bus module (usb) motorola istall0 ? endpoint 0 force stall bit for in token this read/write bit caus es endpoint 0 to retu rn a stall handshake when polled by an in token by the usb host controller. reset clears this bit. 1 = send stall handshake 0 = default pullen ? pull-up enable this read/write bit controls the pull-up option for the usb d? pin if the usb module is enabled. 1 = configure d? pin to have internal pull-up 0 = disconnect d? pin internal pull-up enable2 ? endpoint 2 enable this read/write bi t enables endpoint 2 and al lows the usb to respond to in or out packets addressed to endpoint 2. reset clears this bit. 1 = endpoint 2 is ena bled and can respond to an in or out token 0 = endpoint 2 is disabled enable1 ? endpoint 1 enable this read/write bi t enables endpoint 1 and al lows the usb to respond to in packets addressed to endpoi nt 1. reset clears this bit. 1 = endpoint 1 is enabled and can respond to an in token 0 = endpoint 1 is disabled f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . universal serial bus module (usb) i/o registers mc68hc908jb8mc68hc08jb8mc68HC08JT8 ? rev. 2.1 technical data motorola universal serial bus module (usb) 151 9.8.9 usb control register 4 usb control register 4 di rectly controls the usb data pins d+ and d?. if the fusbo bit, and the usben bit of the usb address register (uaddr) are set, the output buffers of t he usb modules are enabled and the corresponding levels of the usb data pins d+ and d? are equal to the values set by the fdp and the fdm bits. fusbo ? force usb output this read/write bi t enables the usb output buffers. 1 = enables usb output buffers 0 = usb module in normal operation fdp ? force d+ this read/write bit det erminates the out put level of d+. 1 = d+ at output high level 0 = d+ at output low level fdm ? force d? this read/write bit det erminates the out put level of d?. 1 = d? at output high level 0 = d? at output low level note: customers must be very careful w hen setting the ucr4 register. when the fusbo and the us ben bits are set, the usb module is in output mode and it will not re cognize any usb signals including the usb reset signal. the ucr4 register is used for some special applications. customers are not nor mally expected to use this register. address: $001b bit 7654321bit 0 read: 0 0 0 0 0 fusbo fdp fdm write: reset:00000000 = unimplemented figure 9-23. u sb control register 4 (ucr4) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . universal serial bus module (usb) technical data mc68hc908jb8mc68h c08jb8mc68HC08JT8 ? rev. 2.1 152 universal serial bus module (usb) motorola 9.8.10 usb status register 0 r0seq ? endpoint 0 re ceive sequence bit this read-only bit indica tes the type of data packet last received for endpoint 0 (data0 or data1). 1 = data1 token received in last endpoint 0 receive 0 = data0 token received in last endpoint 0 receive setup ? setup token detect bit this read-only bit indi cates that a valid setup token has been received. 1 = last token rece ived for endpoint 0 was a setup token 0 = last token receiv ed for endpoint 0 was not a setup token rp0siz3?rp0siz0 ? endpoint 0 receive data packet size these read-only bits store the number of data bytes received for the last out or setup tr ansaction for endpoint 0. address: $003d bit 7654321bit 0 read: r0seq setup 0 0 rp0siz3 rp0siz2 rp0siz1 rp0siz0 write: reset: unaffected by reset = unimplemented figure 9-24. usb stat us register 0 (usr0) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . universal serial bus module (usb) i/o registers mc68hc908jb8mc68hc08jb8mc68HC08JT8 ? rev. 2.1 technical data motorola universal serial bus module (usb) 153 9.8.11 usb status register 1 r2seq ? endpoint 2 re ceive sequence bit this read-only bit indica tes the type of data packet last received for endpoint 2 (data0 or data1). 1 = data1 token received in last endpoint 2 receive 0 = data0 token received in last endpoint 2 receive txack ? ack tok en transmit bit this read-only bit indica tes that an ack token has been transmitted. this bit is updated at the end of the ep0 data transmission. 1 = last token transmitted fo r endpoint 0 wa s an ack token 0 = last token transmitted for endp oint 0 was not an ack token txnak ? nak tok en transmit bit this read-only bit indica tes that a txnak token has been transmitted. this bit is updated at the end of the ep 0 data transmission. 1 = last token transmitted fo r endpoint 0 wa s a nak token 0 = last token transmitted for endpoint 0 was not a nak token txstl ? stall token transmit bit this read-only bit indica tes that a stall token has been transmitted. this bit is updated at the end of the ep0 data transmission. 1 = last token transmitted for endpoint 0 was a stall token 0 = last token transmitted for endp oint 0 was not a stall token rp2siz3?rp2siz0 ? endpoint 2 receive data packet size these read-only bits store the number of data bytes received for the last out transaction for endpoint 2. address: $003e bit 7654321bit 0 read: r2seq txack txnak txstl rp2siz3 rp2siz2 rp2siz1 rp2siz0 write: reset:u0 0 0uuuu = unimplemented u = unaffected by reset figure 9-25. usb stat us register 1 (usr1) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . universal serial bus module (usb) technical data mc68hc908jb8mc68h c08jb8mc68HC08JT8 ? rev. 2.1 154 universal serial bus module (usb) motorola 9.8.12 usb endpoint 0 data registers ue0rx7?ue0rx0 ? endpoint 0 receive data buffer these read-only bits are serially loaded with out token or setup token data directed at en dpoint 0. the data is received over the usb?s d+ and d? pins. ue0tx7?ue0tx0 ? endpoint 0 transmit data buffer these write-only buffers are loaded by software with data to be sent on the usb bus on the next in token directed at endpoint 0. address: $0020 ue0d0 bit 7654321bit 0 read: ue0r07 ue0r06 ue0r05 ue0r04 ue0r03 ue0r02 ue0r01 ue0r00 write: ue0t07 ue0t06 ue0t05 ue0t 04 ue0t03 ue0t02 ue0t01 ue0t00 reset: unaffected by reset address: $0027 ue0d7 read: ue0r77 ue0r76 ue0r75 ue0r74 ue0r73 ue0r72 ue0r71 ue0r70 write: ue0t77 ue0t76 ue0t75 ue0t 74 ue0t73 ue0t72 ue0t71 ue0t70 reset: unaffected by reset figure 9-26. usb end point 0 data regist ers (ue0d0?ue0d7) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . universal serial bus module (usb) i/o registers mc68hc908jb8mc68hc08jb8mc68HC08JT8 ? rev. 2.1 technical data motorola universal serial bus module (usb) 155 9.8.13 usb endpoint 1 data registers ue1tx7?ue1tx0 ? endpoint 1 trans mit or receive data buffer these write-only buffers are loaded by software with data to be sent on the usb bus on the next in token directed at endpoint 1. address: $0028 ue1d0 bit 7654321bit 0 read: write: ue1t07 ue1t06 ue1t05 ue1t 04 ue1t03 ue1t02 ue1t01 ue1t00 reset: unaffected by reset address: $002f ue1d7 read: write: ue1t77 ue1t76 ue1t75 ue1t 74 ue1t73 ue1t72 ue1t71 ue1t70 reset: unaffected by reset = unimplemented figure 9-27. usb end point 1 data regist ers (ue1d0?ue1d7) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . universal serial bus module (usb) technical data mc68hc908jb8mc68h c08jb8mc68HC08JT8 ? rev. 2.1 156 universal serial bus module (usb) motorola 9.8.14 usb endpoint 2 data registers ue2rx7?ue2rx0 ? endpoint 2 receive data buffer these read-only bits are serially loaded with out token data directed at endpoint 2. the data is received over the usb?s d+ and d? pins. ue2tx7?ue2tx0 ? endpoint 2 transmit data buffer these write-only buffers are loaded by software with data to be sent on the usb bus on the next in token directed at endpoint 2. address: $0030 ue2d0 bit 7654321bit 0 read: ue2r07 ue2r06 ue2r05 ue2r04 ue2r03 ue2r02 ue2r01 ue2r00 write: ue2t07 ue2t06 ue2t05 ue2t 04 ue2t03 ue2t02 ue2t01 ue2t00 reset: unaffected by reset address: $0037 ue2d7 read: ue2r77 ue2r76 ue2r75 ue2r74 ue2r73 ue2r72 ue2r71 ue2r70 write: ue2t77 ue2t76 ue2t75 ue2t 74 ue2t73 ue2t72 ue2t71 ue2t70 reset: unaffected by reset figure 9-28. usb end point 2 data regist ers (ue2d0?ue2d7) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . universal serial bus module (usb) usb interrupts mc68hc908jb8mc68hc08jb8mc68HC08JT8 ? rev. 2.1 technical data motorola universal serial bus module (usb) 157 9.9 usb interrupts the usb module is capabl e of generating interr upts and causing the cpu to execute the usb interrupt se rvice routine. ther e are three types of usb interrupts: end-of-transaction interrupts signify either a completed transaction receive or transmit transaction. resume interrupts signify that t he usb bus is reactivated after having been suspended. end-of-packet interrupts signify that a low-speed end-of-packet signal was detected. all usb interrupts shar e the same interrupt vector. firmware is responsible for determining which interrupt is active. 9.9.1 usb end-of-transaction interrupt there are five possible end- of-transaction interrupts: endpoint 0 or 2 receive endpoint 0, 1 or 2 transmit end-of-transaction in terrupts occur as detailed in the following sections. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . universal serial bus module (usb) technical data mc68hc908jb8mc68h c08jb8mc68HC08JT8 ? rev. 2.1 158 universal serial bus module (usb) motorola 9.9.1.1 receive control endpoint 0 for a control out transaction dire cted at endpoint 0, the usb module will generate an interrupt by setting t he rxd0f flag in the uir0 register. the conditions necessary for the inte rrupt to occur are shown in the flowchart in figure 9-29 . figure 9-29. out token data flow for receive endpoint 0 valid out token received for endpoint 0 error free data packet? no response from usb function set rxd0f to 1 (rxd0ie = 1) no interrupt accept data no response from usb function timeout n set/clear r0seq bit valid data token received for endpoint 0? usb module enabled? (usben = 1) endpoint 0 receive not stalled? (ostall0 = 0) endpoint 0 receive ready to receive? (rx0e = 1) and (rxd0f = 0) receive control endpoint interrupt enabled? valid transaction interrupt generated send stall handshake send nak handshake no response from usb function ignore transaction y y y y y y n n n n n y f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . universal serial bus module (usb) usb interrupts mc68hc908jb8mc68hc08jb8mc68HC08JT8 ? rev. 2.1 technical data motorola universal serial bus module (usb) 159 setup transactions cann ot be stalled by the usb function. a setup received by a control endp oint will clear the is tall0 and ostall0 bits. the conditions for receiving a setup interrupt are shown in figure 9-30 . figure 9-30. setup token data flow for receive endpoint 0 error free data packet? no response from usb function set rxd0f to 1 (rxd0ie = 1) no interrupt accept data n set/clear r0seq bit valid setup token received for endpoint 0? usb module enabled? (usben = 1) endpoint 0 receive ready to receive? (rx0e = 1) and (rxd0f = 0) receive control endpoint interrupt enabled? valid transaction interrupt generated no response from usb function no response from usb function ignore transaction y y y y y n n n set setup bit to 1 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . universal serial bus module (usb) technical data mc68hc908jb8mc68h c08jb8mc68HC08JT8 ? rev. 2.1 160 universal serial bus module (usb) motorola 9.9.1.2 transmit control endpoint 0 for a control in transaction directed at endpoint 0, the usb module will generate an interrupt by setting the tx d0f flag in the ui r1 register. the conditions necessary for the interrupt to occur are shown in the flowchart in figure 9-31 . figure 9-31. in token data flow for transmit endpoint 0 valid in token received for endpoint 0 send stall handshake set txd0f to 1 (txd0ie = 1) no interrupt send data n data pid set by t0seq usb module enabled? (usben = 1) transmit endpoint not stalled by firmware (istall0 = 0)? transmit endpoint ready to transfer? (tx0e = 1) and (txd0f = 0) transmit endpoint interrupt enabled? valid transaction interrupt generated send nak handshake y y y y y n n n n y no response from usb function ack received and no timeout condition occurs? no response from usb function f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . universal serial bus module (usb) usb interrupts mc68hc908jb8mc68hc08jb8mc68HC08JT8 ? rev. 2.1 technical data motorola universal serial bus module (usb) 161 9.9.1.3 transmit endpoint 1 for an in transaction directed at endpoint 1, the usb module will generate an interrupt by setting the txd1f in t he uir1 register. the conditions necessary for the inte rrupt to occur are shown in figure 9-32 . figure 9-32. in token data flow for transmit endpoint 1 valid in token received for endpoint 1 send stall handshake set txd1f to 1 (txd1ie = 1) no interrupt send data n data pid set by t1seq usb module enabled? (usben = 1) transmit endpoint not stalled by firmware (stall1 = 1)? transmit endpoint ready to transfer? (tx1e = 1) and (txd1f = 0) and (ue1tr = 0) transmit endpoint enabled? (enable = 1) transmit endpoint interrupt enabled? valid transaction interrupt generated send nak handshake no response from usb function y y y y y y n n n n n y no response from usb function ack received and no timeout condition occurs? no response from usb function f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . universal serial bus module (usb) technical data mc68hc908jb8mc68h c08jb8mc68HC08JT8 ? rev. 2.1 162 universal serial bus module (usb) motorola 9.9.1.4 transmit endpoint 2 for an in transaction directed at endpoint 2, the usb module will generate an interrupt by setting the txd2f in the uir1 register. 9.9.1.5 receive endpoint 2 for an out transaction directed at endpoint 2, the usb module will generate an interrupt by setting the rxd2f in the uir1 register. 9.9.2 resume interrupt the usb module will generate a cpu interrupt if low-speed bus activity is detected after entering the suspend st ate. a transition of the usb data lines to the non-idle stat e (k state) while in the suspend mode will set the resumf flag in the uir1 register. ther e is no interrupt enable bit for this interrupt source and an in terrupt will be executed if the i-bit in the ccr is cleared. a resume interrupt can only occur while t he mcu is in the suspend mode. 9.9.3 end-of-packet interrupt the usb module ca n generate a usb interr upt upon detection of an end-of-packet signal for low-s peed devices. upon detection of an end-of-packet signal, the usb module sets the eopf bit and will generate a cpu interrupt if the eopie bit in the uir0 register is set. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc908jb8mc68hc08jb8mc68HC08JT8 ? rev. 2.1 technical data motorola monitor rom (mon) 163 technical data ? mc68hc908jb8?mc68hc08jb8?mc68HC08JT8 section 10. monitor rom (mon) 10.1 contents 10.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 10.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 10.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .164 10.4.1 entering monitor mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 10.4.2 baud rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .169 10.4.3 data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 10.4.4 echoing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 10.4.5 break signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 10.4.6 commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 10.5 security. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 10.2 introduction this section describes the monitor rom (mon) and the monitor mode entry methods. the monitor rom allows complete testing of the mcu through a single- wire interface with host com puter. this mode is also used for programming and erasing of flash memory in the mcu. monitor mode entry can be achieved without use of the higher voltage, v dd +v hi , as long as vector addre sses $fffe and $f fff are blank, thus reducing the hardw are requirements for in -circuit programming. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . monitor rom (mon) technical data mc68hc908jb8mc68h c08jb8mc68HC08JT8 ? rev. 2.1 164 monitor rom (mon) motorola 10.3 features features of the monitor rom include the following: normal user-mode pin functionality one pin dedicated to serial co mmunication between monitor rom and host computer standard mark/space non-return -to-zero (nrz) communication with host computer execution of code in ram or flash flash memory security feature 1 flash memory progr amming interface 976 bytes monitor rom code size monitor mode entry wi thout high voltage, v dd +v hi , if reset vector is blank ($fffe and $ffff contain $ff) standard monitor mode ent ry if high voltage, v dd +v hi , is applied to irq 10.4 functional description the monitor rom receives and exec utes commands from a host computer. figure 10-1 shows a example circui t used to enter monitor mode and communicate with a host computer via a standard rs-232 interface. simple monitor commands can access any memory address. in monitor mode, the mcu can execute host-co mputer code in ram while most mcu pins retain norm al operating mode func tions. all communication between the host computer and the m cu is through the pta0 pin. a level-shifting and multiplexing in terface is required between pta0 and the host computer. pta0 is used in a wired-or configuration and requires a pull-up resistor. 1. no security feature is absolutely secure. howe ver, motorola?s strategy is to make reading or copying the flash difficult for unauthorized users. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . monitor rom (mon) functional description mc68hc908jb8mc68hc08jb8mc68HC08JT8 ? rev. 2.1 technical data motorola monitor rom (mon) 165 figure 10-1. moni tor mode circuit + + + + 10m ? mc145407 mc74lcx125 hc908jb8 rst irq osc1 osc2 v ss pta0 3.3v 10 k ? 10k ? 6 5 2 4 3 1 db-25 2 3 7 20 18 17 19 16 15 3.3v v dd 20 pf 20 pf 10 f 10 f 10 f 10 f 1 2 4 7 14 3 0.1 f 6mhz 5 6 pta1 v dd 0.1 f v dd pta2 3.3v 10 k ? pta3 3.3v 10 k ? 10 k ? sw1 a b v dd + v hi sw2 e f (see note 2) notes: 1. affects high voltage entry to monitor mode only (sw2 at position c): sw1: position a ? bus clock = f xclk 2 sw1: position b ? bus clock = f xclk 2. sw2: position c ? high-voltage entry to monitor mode. sw2: position d ? low-voltage entry to monitor mode (with blank reset vector). see section 18 for irq voltage level requirements. 3. sw3: position e ? osc1 directly driven by exter nal oscillator. sw3: position f ? osc1 driven by crystal oscillator circuit. 10k ? v dd v dd (see note 3) (see note 1) e f c d 6mhz sw3 f xclk v reg 4.7 f 0.1 f + f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . monitor rom (mon) technical data mc68hc908jb8mc68h c08jb8mc68HC08JT8 ? rev. 2.1 166 monitor rom (mon) motorola 10.4.1 entering monitor mode table 10-1 shows the pin conditions fo r entering monitor mode. as specified in the table, monitor mode may be ente red after a por and will allow communication at 9600 baud pr ovided one of the fo llowing sets of conditions is met: 1. if irq = v dd + v hi : ? external clock on osc1 is 3mhz ? pta3 = low 2. if irq = v dd + v hi : ? external clock on osc1 is 6mhz ? pta3 = high 3. if $fffe & $ffff is blank (contains $ff): ? external clock on osc1 is 6mhz ?irq = v dd table 10-1. mode entry requirements and options irq $fffe and $ffff pta3 pta2 pta1 pta0 external clock, f xclk bus frequency, f bus comments v dd + v hi x 0011 3mhz 3mhz (f xclk ) high-voltage entry to monitor mode. 9600 baud communication on pta0. cop disabled. v dd + v hi x 1011 6mhz 3mhz (f xclk 2) v dd blank (contain $ff) xxx1 6mhz 3mhz (f xclk 2) low-voltage entry to monitor mode. 9600 baud communication on pta0. cop disabled. v dd not blank xxxx 6mhz 3mhz (f xclk 2) enters user mode. if $fffe and $ffff is blank, mcu will encounter an illegal address reset. notes: 1. pta3 = 0: bypasses the divide-by -two prescaler to sim when using v dd + v hi for monitor mode entry. 2. see section 18. electrical specifications for v dd + v hi voltage level requirements. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . monitor rom (mon) functional description mc68hc908jb8mc68hc08jb8mc68HC08JT8 ? rev. 2.1 technical data motorola monitor rom (mon) 167 if v dd +v hi is applied to irq and pta3 is low upon monitor mode entry ( table 10-1 condition set 1), the bus frequency is a equal to the external clock, f xclk . if pta3 is high with v dd +v hi applied to irq upon monitor mode entry ( table 10-1 condition set 2), the bus frequency is a divide- by-two of the external clock. hold ing the pta3 pin low when entering monitor mode causes a bypass of a divide-by-tw o stage at the oscillator only if v dd +v hi is applied to irq . in this event, th e oscout frequency is equal to the oscxclk frequency. entering monitor mode with v dd +v hi on irq , the cop is disabled as long as v dd +v hi is applied to either the irq or the rst . (see section 8. system integr ation module (sim) for more information on modes of operation.) if entering monito r mode without high voltage on irq and reset vector being blank ($fffe and $ffff) ( table 10-1 condition set 3, where irq applied voltage is v dd ), then all port a pin re quirements and conditions, including the pta3 frequen cy divisor selection, are not in effect. this is to reduce circuit require ments when performing in -circuit programming. entering monitor mode with the reset vector bei ng blank, the cop is always disabled regardles s of the state of irq or the rst . figure 10-2 . shows a simplified diagram of the monitor mode entry when the reset vector is blank and irq = v dd . an external cl ock of 6mhz is required for a baud rate of 9600. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . monitor rom (mon) technical data mc68hc908jb8mc68h c08jb8mc68HC08JT8 ? rev. 2.1 168 monitor rom (mon) motorola figure 10-2. low-voltage moni tor mode entr y flowchart enter monitor mode with the pin co nfiguration shown above by pulling rst low and then high. the rising edge of rst latches monitor mode. once monitor mode is la tched, the values on th e specified pins can change. once out of reset, t he mcu waits for the host to send eight security bytes. (see 10.5 security .) after the security bytes, the mcu sends a break signal (10 consecutiv e logic zeros) to the host, indicating that it is ready to receive a command. the br eak signal also pr ovides a timing reference to allow t he host to determine t he necessary baud rate. in monitor mode, the mc u uses different vector s for reset, swi, and break interrupt. the alternate vectors are in the $fe page instead of the $ff page and allow code execution from the internal monitor firmware instead of user code. is vector blank? por triggered? normal user mode monitor mode execute monitor code no no yes yes por reset f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . monitor rom (mon) functional description mc68hc908jb8mc68hc08jb8mc68HC08JT8 ? rev. 2.1 technical data motorola monitor rom (mon) 169 table 10-2 is a summary of the vector differences between user mode and monitor mode. when the host computer has comple ted downloading code into the mcu ram, the host then sends a run command, whic h executes an rti, which sends control to the address on the stack pointer. 10.4.2 baud rate the communication baud rate is dependa nt on oscillator frequency, f xclk . the state of pta3 also affects ba ud rate if entry to monitor mode is by irq =v dd +v hi . when pta3 is high, the di vide by ratio is 625. if the pta3 pin is at logic zero upon en try into monitor m ode, the divide by ratio is 312. table 10-2. monitor mo de vector differences modes functions cop reset vector high reset vector low break vector high break vector low swi vector high swi vector low user enabled $fffe $ffff $fffc $fffd $fffc $fffd monitor disabled (1) $fefe $feff $fefc $fefd $fefc $fefd notes: 1. if the high voltage (v dd + v hi ) is removed from the irq pin or the rst pin, the sim asserts its cop enable output. the cop is a mask option enabled or disabled by the copd bit in the configuration register. table 10-3. monitor baud rate selection monitor mode entry by: oscillator clock frequency, f clk pta3 baud rate irq = v dd + v hi 3 mhz 0 9600 bps 6 mhz 1 9600 bps 3 mhz 1 4800 bps blank reset vector, irq = v dd 6 mhz x 9600 bps 3 mhz x 4800 bps f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . monitor rom (mon) technical data mc68hc908jb8mc68h c08jb8mc68HC08JT8 ? rev. 2.1 170 monitor rom (mon) motorola 10.4.3 data format communication with the monitor rom is in standard non-return-to-zero (nrz) mark/space data format. (see figure 10-3 and figure 10-4 .) figure 10-3. moni tor data format figure 10-4. sample monitor waveforms the data transmit and receive rate can be anywhere fr om 4800 baud to 28.8k-baud. transmit and receive baud rates must be identical. 10.4.4 echoing as shown in figure 10-5 , the monitor rom immediately echoes each received byte back to the pt a0 pin for error checking. figure 10-5. read transaction any result of a command appears after the ec ho of the last byte of the command. bit 5 start bit bit 0 bit 1 next stop bit start bit bit 2 bit 3 bit 4 bit 6 bit 7 bit 5 start bit bit 0 bit 1 next stop bit start bit bit 2 bit 3 bit 4 bit 6 bit 7 start bit bit 0 bit 1 next stop bit start bit bit 2 $a5 break bit 3 bit 4 bit 5 bit 6 bit 7 addr. high read read addr. high addr. low addr. low data echo sent to monitor result f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . monitor rom (mon) functional description mc68hc908jb8mc68hc08jb8mc68HC08JT8 ? rev. 2.1 technical data motorola monitor rom (mon) 171 10.4.5 break signal a start bit followed by nine low bits is a break signal. (see figure 10-6.) when the monitor receives a break sign al, it drives the pta0 pin high for the duration of tw o bits before echoi ng the break signal. figure 10-6. break transaction 10.4.6 commands the monitor rom uses t he following commands: read (read memory) write (write memory) iread (indexed read) iwrite (indexed write) readsp (read stack pointer) run (run user program) 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 missing stop bit two-stop-bit delay before zero echo f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . monitor rom (mon) technical data mc68hc908jb8mc68h c08jb8mc68HC08JT8 ? rev. 2.1 172 monitor rom (mon) motorola table 10-4. read (r ead memory) command description read byte from memory operand specifies 2-byte address in high byte:low byte order data returned returns contents of specified address opcode $4a command sequence addr. high read read addr. high addr. low addr. low data echo sent to monitor result table 10-5. write (write memory) command description write byte to memory operand specifies 2-byte address in high byte:low byte order; low byte followed by data byte data returned none opcode $49 command sequence addr. high write write addr. high addr. low addr. low data echo sent to monitor data f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . monitor rom (mon) functional description mc68hc908jb8mc68hc08jb8mc68HC08JT8 ? rev. 2.1 technical data motorola monitor rom (mon) 173 note: a sequence of iread or iwrite commands can sequentially access a block of memory over the full 64-kbyte memory map. table 10-6. iread (i ndexed read) command description read next 2 bytes in me mory from last address accessed operand specifies 2-byte address in high byte:low byte order data returned returns contents of next two addresses opcode $1a command sequence data iread iread data echo sent to monitor result table 10-7. iwrite (indexed write) command description write to last address accessed + 1 operand specifies single data byte data returned none opcode $19 command sequence data iwrite iwrite data echo sent to monitor f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . monitor rom (mon) technical data mc68hc908jb8mc68h c08jb8mc68HC08JT8 ? rev. 2.1 174 monitor rom (mon) motorola table 10-8. readsp (read stack pointer) command description reads stack pointer operand none data returned returns stack pointer in high byte:low byte order opcode $0c command sequence sp high readsp readsp sp low echo sent to monitor result table 10-9. run (run u ser program) command description executes rti instruction operand none data returned none opcode $28 command sequence run run echo sent to monitor f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . monitor rom (mon) security mc68hc908jb8mc68hc08jb8mc68HC08JT8 ? rev. 2.1 technical data motorola monitor rom (mon) 175 10.5 security a security feature discourages unaut horized reading of flash locations while in monitor mode. the host can bypass the securi ty feature at monitor mode entry by sending eight security bytes that match the bytes at locations $fff6?$fffd. locati ons $fff6?$fffd contain user- defined data. note: do not leave locati ons $fff6?$fffd blank . for security reasons, program locations $fff6?$fffd even if they are not used for vectors. during monitor mode entry, the mcu waits after the power-on reset for the host to send th e eight security bytes on pi n pta0. if the received bytes match those at location s $fff6?$fffd, the hos t bypasses the security feature and can read al l flash locations and execute code from flash. security remains bypa ssed until a power-on reset occurs. if the reset was not a power-on reset, security remains bypassed and security code entry is not required. (see figure 10-7 .) figure 10-7. monitor mode entry timing byte 1 byte 1 echo byte 2 byte 2 echo byte 8 byte 8 echo command command echo pta0 rst v dd 4096 + 32 oscxclk cycles 24 bus cycles 1 4 1 1 2 1 break notes: 2 = data return delay, 2 bit times 4 = wait 1 bit time before sending next byte. 4 from host from mcu 1 = echo delay, 2 bit times f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . monitor rom (mon) technical data mc68hc908jb8mc68h c08jb8mc68HC08JT8 ? rev. 2.1 176 monitor rom (mon) motorola upon power-on reset, if the receiv ed bytes of the se curity code do not match the data at loca tions $fff6?$fffd, the host fails to bypass the security feature. the mcu remain s in monitor mode, but reading a flash location returns an invalid val ue and trying to exec ute code from flash causes an illegal address reset. after receiving the eight security bytes from the host, the mc u transmits a br eak character, signifying that it is ready to receive a command. note: the mcu does not transmit a break character unti l after the host sends the eight security bytes. to determine whether the security c ode entered is correct, check to see if bit 6 of ram address $ 40 is set. if it is, then the correct security code has been entered and fl ash can be accessed. if the security sequence fails, the device should be reset by a power-on reset and brought up in monitor mode to atte mpt another entry. after failing the security s equence, the flash modul e can also be mass erased by executing an erase routine that was downloaded into internal ram. the mass erase operat ion clears the security code locations so that all eight security bytes become $ff (blank). f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc908jb8mc68hc08jb8mc68HC08JT8 ? rev. 2.1 technical data motorola timer interface module (tim) 177 technical data ? mc68hc908jb8?mc68hc08jb8?mc68HC08JT8 section 11. timer interface module (tim) 11.1 contents 11.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 11.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 11.4 pin name conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 11.5 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .179 11.5.1 tim counter prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 11.5.2 input capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 11.5.3 output compare. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 11.5.3.1 unbuffered output compare . . . . . . . . . . . . . . . . . . . . . 182 11.5.3.2 buffered output com pare . . . . . . . . . . . . . . . . . . . . . . .183 11.5.4 pulse width modulatio n (pwm) . . . . . . . . . . . . . . . . . . . . . 183 11.5.4.1 unbuffered pwm sig nal generation . . . . . . . . . . . . . . . 184 11.5.4.2 buffered pwm signal generation . . . . . . . . . . . . . . . . . 185 11.5.4.3 pwm initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 11.6 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .187 11.7 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 11.7.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .188 11.7.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .188 11.8 tim during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . 188 11.9 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 11.9.1 tim clock pin (pte0/tc lk) . . . . . . . . . . . . . . . . . . . . . . .189 11.9.2 tim channel i/o pins (pte1/tch0:pte2/ tch1) . . . . . . . 189 11.10 i/o registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 11.10.1 tim status and control register . . . . . . . . . . . . . . . . . . . . 190 11.10.2 tim counter registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 11.10.3 tim counter modulo r egisters . . . . . . . . . . . . . . . . . . . . . 193 11.10.4 tim channel status and control registers . . . . . . . . . . . . 194 11.10.5 tim channel registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module (tim) technical data mc68hc908jb8mc68h c08jb8mc68HC08JT8 ? rev. 2.1 178 timer interface module (tim) motorola 11.2 introduction this section describes the timer inte rface module (tim2, version b). the tim is a 2-channel time r that provides a timi ng reference with input capture, output compare, and pul se-width-modulation functions. figure 11-1 is a block diagram of the tim. 11.3 features features of the tim include: two input capture/ou tput compare channels ? rising-edge, falling-edge, or any-edge input capture trigger ? set, clear, or toggle output compare action buffered and unbuffered pulse width modulation (pwm) signal generation programmable tim clock input ? 7-frequency internal bus cl ock prescaler selection ? external tim clock input (bus frequency 2 maximum) free-running or modul o up-count operation toggle any channel pin on overflow tim counter stop and reset bits 11.4 pin name conventions the tim share three i/o pi ns with three port e i/ o pins. the full name of the tim i/o pin is listed in table 11-1 . the generic pin name appear in the text that follows. table 11-1. tim pi n name conventions tim generic pin names: tclk tch0 tch1 full tim pin names: pte0/tclk pte1/tch0 pte2/tch1 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module (tim) functional description mc68hc908jb8mc68hc08jb8mc68HC08JT8 ? rev. 2.1 technical data motorola timer interface module (tim) 179 11.5 functional description figure 11-1 shows the structure of the tim. the central component of the tim is the 16-bit tim counter that can operate as a free-running counter or a modulo up-counter. the tim counter provides the timing reference for the input capture and output co mpare functions. the tim counter modulo registers, tmodh:tmodl, contro l the modulo value of the tim counter. software can read th e tim counter value at any time without affecting the counting sequence. the two tim channels are program mable independently as input capture or output compare channels. figure 11-1. tim block diagram prescaler prescaler select 16-bit comparator ps2 ps1 ps0 16-bit comparator 16-bit latch tch0h:tch0l ms0a els0b els0a tof toie 16-bit comparator 16-bit latch tch1h:tch1l channel 0 channel 1 tmodh:tmodl trst tstop tov0 ch0ie ch0f els1b els1a tov1 ch1ie ch1max ch1f ch0max ms0b 16-bit counter internal bus ms1a internal bus clock tch1 tch0 interrupt logic port logic interrupt logic interrupt logic port logic tclk f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module (tim) technical data mc68hc908jb8mc68h c08jb8mc68HC08JT8 ? rev. 2.1 180 timer interface module (tim) motorola addr. register name bit 7654321bit 0 $000a tim status and control register (tsc) read: tof toie tstop 00 ps2 ps1 ps0 write: 0 trst reset:00100000 $000c tim counter register high (tcnth) read: bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 write: reset:00000000 $000d tim counter register low (tcntl) read: bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 write: reset:00000000 $000e tim counter modulo register high (tmodh) read: bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 write: reset:11111111 $000f tim counter modulo register low (tmodl) read: bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 write: reset:11111111 $0010 tim channel 0 status and control register (tsc0) read: ch0f ch0ie ms0b ms0a els0b els0a tov0 ch0max write: 0 reset:00000000 $0011 tim channel 0 register high (tch0h) read: bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 write: reset: indeterminate after reset $0012 tim channel 0 register low (tch0l) read: bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 write: reset: indeterminate after reset $0013 tim channel 1 status and control register (tsc1) read: ch1f ch1ie 0 ms1a els1b els1a tov1 ch1max write: 0 reset:00000000 = unimplemented figure 11-2. tim i/o register summary f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module (tim) functional description mc68hc908jb8mc68hc08jb8mc68HC08JT8 ? rev. 2.1 technical data motorola timer interface module (tim) 181 11.5.1 tim counter prescaler the tim clock source can be one of th e seven prescaler outputs or the tim clock pin, pte0/tclk. the pre scaler generates seven clock rates from the internal bus cl ock. the prescaler select bits, ps[2:0], in the tim status and control register (tsc ) select the tim clock source. 11.5.2 input capture with the input capture function, the tim can capture the time at which an external event occurs. when an acti ve edge occurs on the pin of an input capture channel, the tim latches the cont ents of the tim counter into the tim channel registers, tc hxh:tchxl. the polarity of the active edge is programmable. input captures can generate tim cpu interrupt requests. 11.5.3 output compare with the output compare function, the tim can gener ate a periodic pulse with a programmable polarity, duration, and fr equency. when the counter reaches the value in the r egisters of an output compare channel, the tim can set, clear, or toggle the channel pin. output compares can generate tim cpu interrupt requests. $0014 tim channel 1 register high (tch1h) read: bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 write: reset: indeterminate after reset $0015 tim channel 1 register low (tch1l) read: bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 write: reset: indeterminate after reset = unimplemented figure 11-2. tim i/o register summary f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module (tim) technical data mc68hc908jb8mc68h c08jb8mc68HC08JT8 ? rev. 2.1 182 timer interface module (tim) motorola 11.5.3.1 unbuffered output compare any output compare channel can generate unbuffered output compare pulses as described in 11.5.3 output compare . the pulses are unbuffered because changing the output compare value requires writing the new value over the old value currently in the tim channel registers. an unsynchronized write to the tim channel regist ers to change an output compare value could cause incorrect operati on for up to two counter overflow periods. for exampl e, writing a new value before the counter reaches the old value but after the c ounter reaches the new value prevents any compare during that counter overflow period. also, using a tim overflow interrupt rout ine to write a new, smaller output compare value may caus e the compare to be missed. the tim may pass the new value befor e it is written. use the following methods to synch ronize unbuffered changes in the output compare va lue on channel x: when changing to a smaller va lue, enable channel x output compare interrupts and write the new value in the output compare interrupt routine. the output compare interrupt occurs at the end of the current output compare pulse . the interrupt routine has until the end of the counter overflow period to write the new value. when changing to a larger output compare val ue, enable tim overflow interrupts a nd write the new value in the tim overflow interrupt routine. the tim overflow interrupt occurs at the end of the current counter overflow perio d. writing a larger value in an output compare interrupt routine (at the end of the current pulse) could cause two output compares to occur in the same counter overflow period. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module (tim) functional description mc68hc908jb8mc68hc08jb8mc68HC08JT8 ? rev. 2.1 technical data motorola timer interface module (tim) 183 11.5.3.2 buffered output compare channels 0 and 1 can be linked to form a buffered output compare channel whose output appears on the pte1/tch0 pin. the tim channel registers of the lin ked pair alternatel y control the output. setting the ms0b bit in tim channel 0 status and control register (tsc0) links channel 0 and channel 1. the output comp are value in the tim channel 0 registers initially controls the output on t he pte1/tch0 pin. writing to the tim c hannel 1 registers enables the tim channel 1 registers to synchronously control the output after the ti m overflows. at each subsequent overflow, t he tim channel registers (0 or 1) that control the output are the ones written to last. tsc0 controls and monitors the buffered output compare function, and tim channel 1 status and control register (tsc1) is unused. while the ms0b bit is set, the channel 1 pin, pte2/tch1, is available as a general-purpose i/o pin. note: in buffered output compare operati on, do not write new output compare values to the currently active channel registers. user software should track the currently active channel to prevent writing a new value to the active channel. writing to the active channel registers is the same as generating unbuffered output compares. 11.5.4 pulse width modulation (pwm) by using the toggle-on-overflow f eature with an output compare channel, the tim can generate a pwm signal. the value in the tim counter modulo registers determi nes the period of th e pwm signal. the channel pin toggles when the counter reaches the value in the tim counter modulo registers. the time between ov erflows is the period of the pwm signal. as figure 11-3 shows, the output compar e value in the tim channel registers determines t he pulse width of the pwm signal. the time between overflow and output compare is the pulse width. program the tim to clear the channel pin on outpu t compare if the state of the pwm pulse is logic 1. program the tim to set the pi n if the state of the pwm pulse is logic 0. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module (tim) technical data mc68hc908jb8mc68h c08jb8mc68HC08JT8 ? rev. 2.1 184 timer interface module (tim) motorola figure 11-3. pwm peri od and pulse width the value in the tim counter modu lo registers and the selected prescaler output determines the frequency of the pwm output. the frequency of an 8-bit pwm signal is va riable in 256 in crements. writing $00ff (255) to the ti m counter modulo regi sters produces a pwm period of 256 times the in ternal bus clock period if the prescaler select value is 000 (see 11.10.1 tim status and control register ). the value in the tim chan nel registers determines the pulse width of the pwm output. the pulse width of an 8-bit pwm sign al is variable in 256 increments. writing $008 0 (128) to the tim c hannel registers produces a duty cycle of 128 /256 or 50%. 11.5.4.1 unbuffered pwm signal generation any output compare channel can generate unbuffered pwm pulses as described in 11.5.4 pulse width modulation (pwm) . the pulses are unbuffered because changing the pulse width requires writing the new pulse width value over the old value currentl y in the tim channel registers. an unsynchronized write to the ti m channel registers to change a pulse width value could cause incorrect oper ation for up to two pwm periods. for example, writing a new value before the counter reaches the old value but after the counter reaches the new value prevents any compare during that pwm period. also, using a tim overflow inte rrupt routine to write a new, smaller pulse width value may caus e the compare to be missed. the tim may pass the new value before it is written. ptex/tchxa period pulse width overflow overflow overflow output compare output compare output compare f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module (tim) functional description mc68hc908jb8mc68hc08jb8mc68HC08JT8 ? rev. 2.1 technical data motorola timer interface module (tim) 185 use the following methods to synch ronize unbuffered changes in the pwm pulse width on channel x: when changing to a shorter pulse width, enable channel x output compare interrupts and write the new value in the output compare interrupt routine. the output compare interrupt occurs at the end of the current pu lse. the interrupt routi ne has until the end of the pwm period to write the new value. when changing to a longer pulse width, enable tim overflow interrupts and write the new value in the tim overflow interrupt routine. the tim overflow interrupt occurs at the end of the current pwm period. writing a larger val ue in an output compare interrupt routine (at the end of the current pulse) c ould cause two output compares to occur in the same pwm period. note: in pwm signal generation , do not program the pw m channel to toggle on output compare. toggling on output compare prevents reliable 0% duty cycle generation and removes the ability of the channel to self- correct in the event of software error or noise. toggling on output compare also can cause incorr ect pwm signal generation when changing the pwm pulse width to a new, much larger value. 11.5.4.2 buffered pwm signal generation channels 0 and 1 can be linked to form a buffered pwm channel whose output appears on the pte1 /tch0 pin. the tim channel registers of the linked pair alternatel y control the pulse width of the output. setting the ms0b bit in tim channel 0 status and control register (tsc0) links channel 0 and channel 1. the tim channel 0 registers initially control the pulse width on the pte1/tch0 pin. writing to the tim channel 1 registers ena bles the tim channel 1 registers to synchronously control the pulse width at the beginning of the next pwm period. at each subsequent overflow, the tim channel registers (0 or 1) that control the pulse wi dth are the ones wr itten to last. tsc0 controls and monitors the buffered pwm func tion, and tim channel 1 status and control register (tsc1) is unused. while the ms 0b bit is set, the channel 1 pin, pte2/tch1, is availabl e as a general-pur pose i/o pin. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module (tim) technical data mc68hc908jb8mc68h c08jb8mc68HC08JT8 ? rev. 2.1 186 timer interface module (tim) motorola note: in buffered pwm signal gener ation, do not write new pulse width values to the currently active channel registers. user so ftware should track the currently active channel to prevent writing a new value to the active channel. writing to the active c hannel registers is the same as generating unbuffer ed pwm signals. 11.5.4.3 pwm initialization to ensure correct operation when gen erating unbuffered or buffered pwm signals, use this initialization procedure: 1. in the tim status and control register (tsc): a. stop the tim counter by se tting the tim stop bit, tstop. b. reset the tim counter and pre scaler by setting the tim reset bit, trst. 2. in the tim counter modulo regi sters (tmodh:tmodl), write the value for the required pwm period. 3. in the tim channel x registers (t chxh:tchxl), write the value for the required pulse width. 4. in tim channel x status and control register (tscx): a. write 0:1 (for unbuffered outp ut compare or pwm signals) or 1:0 (for buffered output com pare or pwm si gnals) to the mode select bits, msxb:msxa. (see table 11-3 .) b. write 1 to the toggle- on-overflow bit, tovx. c. write 1:0 (to clear output on co mpare) or 1:1 (to set output on compare) to the edge/level se lect bits, elsxb:elsxa. the output action on compare must force the output to the complement of the pulse width level. (see table 11-3 .) note: in pwm signal generation , do not program the pw m channel to toggle on output compare. toggling on output compare prevents reliable 0% duty cycle generation and removes the ability of the channel to self- correct in the event of software error or noise. toggling on output compare can also cause incorr ect pwm signal generation when changing the pwm pulse width to a new, much larger value. 5. in the tim status control regist er (tsc), clear t he tim stop bit, tstop. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module (tim) interrupts mc68hc908jb8mc68hc08jb8mc68HC08JT8 ? rev. 2.1 technical data motorola timer interface module (tim) 187 setting ms0b links chann els 0 and 1 and configur es them for buffered pwm operation. the tim channel 0 r egisters (tch0h:tch0l) initially control the buffered pwm output. tim status contro l register 0 (tscr0) controls and monitors the pwm signal from the linked channels. ms0b takes priority over ms0a. clearing the toggle-on-ove rflow bit, tovx, inhibi ts output toggles on tim overflows. subsequent outpu t compares try to forc e the output to a state it is already in and have no effect . the result is a 0% duty cycle output. setting the channel x maximum duty cycle bit (chxmax) and setting the tovx bit generates a 100% duty cycle output. (see 11.10.4 tim channel status and c ontrol registers .) 11.6 interrupts the following tim sources can generate interrupt requests: tim overflow flag (tof) ? th e tof bit is set when the tim counter reaches the modulo value programmed in the tim counter modulo registers. the tim overfl ow interrupt enable bit, toie, enables tim overflow cpu interr upt requests. tof and toie are in the tim status and control register. tim channel flags ( ch1f:ch0f) ? the chxf bi t is set when an input capture or output compar e occurs on channel x. channel x tim cpu interrupt requests ar e controlled by the channel x interrupt enable bit, chxie. c hannel x tim cpu interrupt requests are enabled when chxi e = 1. chxf and ch xie are in the tim channel x status and control register. 11.7 low-power modes the wait and stop in structions put the mcu in low power- consumption standby modes. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module (tim) technical data mc68hc908jb8mc68h c08jb8mc68HC08JT8 ? rev. 2.1 188 timer interface module (tim) motorola 11.7.1 wait mode the tim remains active after the executi on of a wait instru ction. in wait mode the tim registers are not accessible by the cpu. any enabled cpu interrupt request from the tim can bring the mcu out of wait mode. if tim functions are not required during wait mode, reduce power consumption by stopping the tim befor e executing the wait instruction. 11.7.2 stop mode the tim is inactive after the executi on of a stop instru ction. the stop instruction does no t affect register conditions or the state of the tim counter. tim operation resumes when the mcu exits stop mode after an external interrupt. 11.8 tim during break interrupts a break interrupt st ops the tim counter. the system integration module (sim) c ontrols whether status bits in other modules can be cleared during th e break state. the bcfe bit in the break flag control regi ster (bfcr) enables software to clear status bits during the break state. (see 8.8.3 break flag control register .) to allow software to clear status bi ts during a break interrupt, write a logic 1 to the bcfe bit. if a status bi t is cleared during t he break state, it remains cleared when the m cu exits the break state. to protect status bits du ring the break state, writ e a logic 0 to the bcfe bit. with bcfe at logic 0 (its defaul t state), software can read and write i/o registers during the break state wi thout affecting status bits. some status bits have a 2-st ep read/write clearing proced ure. if software does the first step on such a bit before the break, the bit cannot change during the break state as long as bcfe is at logic 0. after the break, doing the second step clears the status bit. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module (tim) i/o signals mc68hc908jb8mc68hc08jb8mc68HC08JT8 ? rev. 2.1 technical data motorola timer interface module (tim) 189 11.9 i/o signals port e shares three of its pins with the tim. pt e0/tclk is an external clock input to the tim prescaler. the two tim channel i/o pins are pte1/tch0 and pte2/tch1. 11.9.1 tim clock pin (pte0/tclk) pte0/tclk is an external clock input that can be the clock source for the tim counter instead of the presca led internal bus cl ock. select the pte0/tclk input by writing logic 1s to the three presca ler select bits, ps[2:0]. (see 11.10.1 tim status and control register .) the minimum tclk pulse width, tclk lmin or tclk hmin , is: the maximum tclk frequency is: bus frequency 2 pte0/tclk is available as a general -purpose i/o pin when not used as the tim clock input. when the pte0/t clk pin is the tim clock input, it is an input regardless of the state of the ddre0 bit in data direction register e. 11.9.2 tim channel i/o pins (pte1/tch0:pte2/tch1) each channel i/o pin is progr ammable independently as an input capture pin or an output compare pin. pte1/tch0 can be configured as buffered output compare or buffered pwm pins. 11.10 i/o registers the following i/o registers control and monitor operation of the tim: tim status and control register (tsc) tim counter registers (tcnth:tcntl) tim counter modulo registers (tmodh:tmodl) tim channel status and con trol registers (tsc0 and tsc1) tim channel registers (tch 0h:tch0l and tch1h:tch1l) 1 bus frequency ------------------ ------------------- t su + f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module (tim) technical data mc68hc908jb8mc68h c08jb8mc68HC08JT8 ? rev. 2.1 190 timer interface module (tim) motorola 11.10.1 tim status and control register the tim status and control register: enables tim overflow interrupts flags tim overflows stops the tim counter resets the tim counter prescales the tim counter clock tof ? tim overflow flag bit this read/write flag is set when t he tim counter reaches the modulo value programmed in the tim counter modulo registers. clear tof by reading the tim status and control register w hen tof is set and then writing a logic 0 to to f. if another tim overfl ow occurs before the clearing sequence is co mplete, then writing logic 0 to tof has no effect. therefore, a tof interrupt request cannot be lost due to inadvertent clearing of tof. rese t clears the tof bit. writing a logic 1 to tof has no effect. 1 = tim counter has reached modulo value 0 = tim counter has not reached modulo value toie ? tim overflow interrupt enable bit this read/write bi t enables tim overflow in terrupts when the tof bit becomes set. reset cl ears the toie bit. 1 = tim overflow interrupts enabled 0 = tim overflow interrupts disabled address: $000a bit 7654321bit 0 read: tof toie tstop 00 ps2 ps1 ps0 write: 0 trst reset: 00100000 = unimplemented figure 11-4. tim st atus and control register (tsc) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module (tim) i/o registers mc68hc908jb8mc68hc08jb8mc68HC08JT8 ? rev. 2.1 technical data motorola timer interface module (tim) 191 tstop ? tim stop bit this read/write bit stop s the tim counter. c ounting resumes when tstop is cleared. reset sets t he tstop bit, stopping the tim counter until software clears the tstop bit. 1 = tim counter stopped 0 = tim counter active note: do not set the tstop bit before enteri ng wait mode if the tim is required to exit wait mode. trst ? tim reset bit setting this write-only bit resets the tim counter and the tim prescaler. setting trst has no ef fect on any other registers. counting resumes from $0000 . trst is cleared automatically after the tim counter is reset and always r eads as logic 0. reset clears the trst bit. 1 = prescaler and tim counter cleared 0 = no effect note: setting the tstop and trst bits simultaneously stops the tim counter at a value of $0000. ps[2:0] ? prescaler select bits these read/write bits select either the pte0/tclk pin or one of the seven prescaler outputs as the input to the tim counter as table 11-2 shows. reset clear s the ps[2:0] bits. table 11-2. pres caler selection ps2 ps1 ps0 tim clock source 0 0 0 internal bus clock 1 0 0 1 internal bus clock 2 0 1 0 internal bus clock 4 0 1 1 internal bus clock 8 1 0 0 internal bus clock 16 1 0 1 internal bus clock 32 1 1 0 internal bus clock 64 1 1 1 pte0/tclk f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module (tim) technical data mc68hc908jb8mc68h c08jb8mc68HC08JT8 ? rev. 2.1 192 timer interface module (tim) motorola 11.10.2 tim counter registers the two read-only tim counter register s contain the high and low bytes of the value in the ti m counter. reading the high byte (tcnth) latches the contents of t he low byte (tcntl) into a buffer. subsequent reads of tcnth do not affect the latched tc ntl value until tcntl is read. reset clears the tim counter registers. setting the tim reset bit (trst) also clears the tim counter registers. note: if you read tcnth during a break interrupt, be sure to unlatch tcntl by reading tcntl before exiting the break interrupt. otherwise, tcntl retains the value latc hed during the break. tcnth address: $000c bit 7654321bit 0 read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset:00000000 tcntl address: $000d bit 7654321bit 0 read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset:00000000 = unimplemented figure 11-5. tim counter registers (tcnth:tcntl) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module (tim) i/o registers mc68hc908jb8mc68hc08jb8mc68HC08JT8 ? rev. 2.1 technical data motorola timer interface module (tim) 193 11.10.3 tim counter modulo registers the read/write tim modulo registers contain the modul o value for the tim counter. when the tim counter reaches t he modulo value, the overflow flag (tof) becomes set, and the tim counter resumes counting from $0000 at the next timer clock. writing to the high byte (tmodh) inhibits the tof bit and overflow inte rrupts until the low byte (tmodl) is written. reset sets the ti m counter modulo registers. note: reset the tim counter bef ore writing to the tim counter modulo registers. tmodh address: $000e bit 7654321bit 0 read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset:11111111 tmodl address: $000f bit 7654321bit 0 read: bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 write: reset:11111111 figure 11-6. tim counter m odulo registers (tmodh:tmodl) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module (tim) technical data mc68hc908jb8mc68h c08jb8mc68HC08JT8 ? rev. 2.1 194 timer interface module (tim) motorola 11.10.4 tim channel status and control registers each of the tim channel status and control regi sters does the following: flags input captures and output compares enables input capture and output compare interrupts selects input capture, output compare, or pwm operation selects high, low, or t oggling output on output compare selects rising edge, fall ing edge, or any edge as the active input capture trigger selects output toggl ing on tim overflow selects 0% and 1 00% pwm duty cycle selects buffered or unbuffer ed output compare/pwm operation tsc0 address: $0010 bit 7654321bit 0 read: ch0f ch0ie ms0b ms0a els0b els0a tov0 ch0max write: 0 reset:00000000 tsc1 address: $0013 bit 7654321bit 0 read: ch1f ch1ie 0 ms1a els1b els1a tov1 ch1max write: 0 reset:00000000 = unimplemented figure 11-7. tim channel status and c ontrol registers (tsc0:tsc1) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module (tim) i/o registers mc68hc908jb8mc68hc08jb8mc68HC08JT8 ? rev. 2.1 technical data motorola timer interface module (tim) 195 chxf ? chann el x flag bit when channel x is an inpu t capture channel, this read/write bit is set when an active edge occurs on the channel x pin. when channel x is an output compare channel, chxf is set when the value in the tim counter registers matche s the value in the ti m channel x registers. when tim cpu interrupt requests ar e enabled (chxie = 1), clear chxf by reading the tim channel x status an d control register with chxf set and then writ ing a logic 0 to chxf . if another interrupt request occurs before the clearing sequence is complete, then writing logic 0 to chxf has no effect. ther efore, an interr upt request cannot be lost due to inadver tent clearing of chxf. reset clears the chxf bit. writing a logic 1 to chxf has no effect. 1 = input capture or out put compare on channel x 0 = no input capture or output compare on channel x chxie ? channel x in terrupt enable bit this read/write bi t enables tim cpu interrupt service requests on channel x. reset cl ears the chxie bit. 1 = channel x cpu inte rrupt requests enabled 0 = channel x cpu interr upt requests disabled msxb ? mode select bit b this read/write bit sele cts buffered output co mpare/pwm operation. msxb exists only in the tim channel 0 status and control register. setting ms0b disables the channel 1 status and control register and reverts tch1 to gen eral-purpose i/o. reset clears the msxb bit. 1 = buffered output com pare/pwm operation enabled 0 = buffered output compar e/pwm operation disabled msxa ? mode select bit a when elsxb:elsxa 0:0, this read/write bi t selects either input capture operation or unbuffered output compare/pwm operation. see table 11-3 . 1 = unbuffered output compare/pwm operation 0 = input capt ure operation f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module (tim) technical data mc68hc908jb8mc68h c08jb8mc68HC08JT8 ? rev. 2.1 196 timer interface module (tim) motorola when elsxb:elsxa = 0:0, this read/wr ite bit selects the initial output level of the tchx pin. (see table 11-3 .) reset clears the msxa bit. 1 = initial output level low 0 = initial output level high note: before changing a channel function by writing to the msxb or msxa bit, set the tstop and trst bi ts in the tim status and control register (tsc). elsxb and elsxa ? edge/level select bits when channel x is an i nput capture channel, th ese read/write bits control the active edge- sensing logic on channel x. when channel x is an output co mpare channel, elsxb and elsxa control the channel x output beh avior when an output compare occurs. when elsxb and elsxa are both cl ear, channel x is not connected to port e, and pin ptex/tchx is av ailable as a gener al-purpose i/o pin. table 11-3 shows how elsxb and elsxa work. reset clears the elsxb and elsxa bits. table 11-3. mode, edge, and level selection msxb msxa elsxb elsxa mode configuration x000 output preset pin under port control; initial output level high x100 pin under port control; initial output level low 0001 input capture capture on rising edge only 0010 capture on fa lling edge only 0011 capture on rising or fa lling edge 0101 output compare or pwm toggle output on compare 0110 clear output on compare 0111 set output on compare 1x01buffered output compare or buffered pwm toggle output on compare 1 x 1 0 clear output on compare 1 x 1 1 set output on compare f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module (tim) i/o registers mc68hc908jb8mc68hc08jb8mc68HC08JT8 ? rev. 2.1 technical data motorola timer interface module (tim) 197 note: before enabling a tim ch annel register for input capture operation, make sure that the ptex/tch x pin is stable for at least two bus clocks. tovx ? toggle-on-overflow bit when channel x is an output compar e channel, this read/write bit controls the behavior of the channel x output when t he tim counter overflows. when channel x is an i nput capture channel, tovx has no effect. reset clear s the tovx bit. 1 = channel x pin toggle s on tim counter overflow 0 = channel x pin does not t oggle on tim counter overflow note: when tovx is set, a tim counter overflow takes precedence over a channel x output compare if bot h occur at the same time. chxmax ? channel x ma ximum duty cycle bit when the tovx bit is at logic 1, setting the chxmax bit forces the duty cycle of buffered and unbuffe red pwm signals to 100%. as figure 11-8 shows, the chxmax bit takes effect in the cycle after it is set or cleared. the output stays at the 100% duty cycle level until the cycle after chxmax is cleared. figure 11-8. chxmax latency output overflow ptex/tchx period chxmax overflow overflow overflow overflow compare output compare output compare output compare f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module (tim) technical data mc68hc908jb8mc68h c08jb8mc68HC08JT8 ? rev. 2.1 198 timer interface module (tim) motorola 11.10.5 tim channel registers these read/write registers contain the captured tim counter value of the input capture function or the outp ut compare value of the output compare function. the state of the tim channel register s after reset is unknown. in input capture mode (m sxb:msxa = 0:0), reading the high byte of the tim channel x registers (t chxh) inhibits input c aptures until the low byte (tchxl) is read. in output compare mode (msxb:msxa 0:0), writing to the high byte of the tim channel x regist ers (tchxh) inhibits out put compares until the low byte (tchxl) is written. tch0h address: $0011 bit 7654321bit 0 read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: indeterminate after reset tch0l address: $0012 bit 7654321bit 0 read: bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 write: reset: indeterminate after reset tch1h address: $0014 bit 7654321bit 0 read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: indeterminate after reset tch1l address: $0015 bit 7654321bit 0 read: bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 write: reset: indeterminate after reset figure 11-9. tim channel re gisters (tch0h/l:tch1h/l) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc908jb8mc68hc08jb8mc68HC08JT8 ? rev. 2.1 technical data motorola input/output ports (i/o) 199 technical data ? mc68hc908jb8?mc68hc08jb8?mc68HC08JT8 section 12. input/output ports (i/o) 12.1 contents 12.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 12.3 port a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 12.3.1 port a data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 12.3.2 data direction register a. . . . . . . . . . . . . . . . . . . . . . . . . . 203 12.4 port b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 12.4.1 port b data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 12.4.2 data direction register b. . . . . . . . . . . . . . . . . . . . . . . . . . 205 12.5 port c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 12.5.1 port c data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 12.5.2 data direction register c. . . . . . . . . . . . . . . . . . . . . . . . . . 208 12.6 port d . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 12.6.1 port d data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 12.6.2 data direction register d. . . . . . . . . . . . . . . . . . . . . . . . . . 211 12.7 port e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 12.7.1 port e data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 12.7.2 data direction register e. . . . . . . . . . . . . . . . . . . . . . . . . . 215 12.8 port options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 12.8.1 port option control register . . . . . . . . . . . . . . . . . . . . . . .217 12.2 introduction thirty-seven (37) bidirect ional input-output (i/o) pi ns form five parallel ports. all i/o pins are progr ammable as inputs or outputs. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . input/output ports (i/o) technical data mc68hc908jb8mc68h c08jb8mc68HC08JT8 ? rev. 2.1 200 input/output ports (i/o) motorola note: connect any unused i/o pins to an a ppropriate logic level, either v reg or v ss . although the i/o po rts do not require te rmination for proper operation, termination reduces e xcess current consumption and the possibility of el ectrostatic damage. addr.register name bit 7654321bit 0 $0000 port a data register (pta) read: pta7 pta6 pta5 pta4 pta3 pta2 pta1 pta0 write: reset: unaffected by reset $0001 port b data register (ptb) read: ptb7 ptb6 ptb5 ptb4 ptb3 ptb2 ptb1 ptb0 write: reset: unaffected by reset $0002 port c data register (ptc) read: ptc7 ptc6 ptc5 ptc4 ptc3 ptc2 ptc1 ptc0 write: reset: unaffected by reset $0003 port d data register (ptd) read: ptd7 ptd6 ptd5 ptd4 ptd3 ptd2 ptd1 ptd0 write: reset: unaffected by reset $0004 data direction register a (ddra) read: ddra7 ddra6 ddra5 ddra4 ddra3 ddra2 ddra1 ddra0 write: reset:0*0000000 * ddra7 bit is reset by por or lvi reset only. $0005 data direction register b (ddrb) read: ddrb7 ddrb6 ddrb5 ddrb4 ddrb3 ddrb2 ddrb1 ddrb0 write: reset:00000000 $0006 data direction register c (ddrc) read: ddrc7 ddrc6 ddrc5 ddrc4 ddrc3 ddrc2 ddrc1 ddrc0 write: reset:00000000 $0007 data direction register d (ddrd) read: ddrd7 ddrd6 ddrd5 ddrd4 ddrd3 ddrd2 ddrd1 ddrd0 write: reset:00000000 $0008 port e data register (pte) read: 0 0 0 pte4 pte3 pte2 pte1 pte0 write: reset: unaffected by reset = unimplemented figure 12-1. i/o port register summary f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . input/output ports (i/o) introduction mc68hc908jb8mc68hc08jb8mc68HC08JT8 ? rev. 2.1 technical data motorola input/output ports (i/o) 201 $0009 data direction register e (ddre) read: 0 0 0 ddre4 ddre3 ddre2 ddre1 ddre0 write: reset:00000000 $001d port option control register (pocr) read: pte20p ptdldd ptdildd pte4p pte3p pcp pbp pap write: reset:00000000 table 12-1. port contro l register bits summary port bit ddr module control pin module register control bit a 0 ddra0 kbi kbier ($0017) kbie0 pta0/kba0 1 ddra1 kbie1 pta1/kba1 2 ddra2 kbie2 pta2/kba2 3 ddra3 kbie3 pta3/kba3 4 ddra4 kbie4 pta4/kba4 5 ddra5 kbie5 pta5/kba5 6 ddra6 kbie6 pta6/kba6 7 ddra7 kbie7 pta7/kba7 b 0?7 ddrb[0:7] ? ? ? ptb0?ptb7 c 0?7 ddrc[0:7] ? ? ? ptc0?ptc7 d 0?7 ddrd[0:7] ? ? ? ptd0?ptd7 e 0 ddre0 tim tsc ($000a) ps[2:0] pte0/tclk 1 ddre1 tsc0 ($0010) els0b:els0a pte1/tch0 2 ddre2 tsc1 ($0013) els1b:els1a pte2/tch1 3 ddre3 usb uaddr ($0038) usben pte3/d+ 4 ddre4 pte4/d? addr.register name bit 7654321bit 0 = unimplemented figure 12-1. i/o port register summary f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . input/output ports (i/o) technical data mc68hc908jb8mc68h c08jb8mc68HC08JT8 ? rev. 2.1 202 input/output ports (i/o) motorola 12.3 port a port a is an 8-bit gener al-purpose bidirectional i/o port with software configurable pullups, and it shares its pins with the keyboard interrupt module (kbi). 12.3.1 port a data register the port a data register co ntains a data latch for each of the eight port a pins. pta[7:0] ? port a data bits these read/write bits are software programmable. data direction of each port a pin is under the control of the corresponding bit in data direction register a. reset has no effect on port a data. the port a pullup enable bit, pap, in the port option control register (pocr) enables pullups on port a pins if t he respective pin is configured as an input. (see 12.8 port options .) kba7 ?kba0 ? keyboard interrupts the keyboard interrupt enable bits , kbie7?kbie0, in the keyboard interrupt enable register (kbier), enable the port a pins as external interrupt pins. (see section 14. keyboard in terrupt module (kbi) .) address: $0000 bit 7654321bit 0 read: pta7 pta6 pta5 pta4 pta3 pta2 pta1 pta0 write: reset: unaffected by reset alternative function: kba7 kba6 kba5 kba4 kba3 kba2 kba1 kba0 additional function: optional pullup optional pullup optional pullup optional pullup optional pullup optional pullup optional pullup optional pullup figure 12-2. port a data register (pta) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . input/output ports (i/o) port a mc68hc908jb8mc68hc08jb8mc68HC08JT8 ? rev. 2.1 technical data motorola input/output ports (i/o) 203 12.3.2 data direction register a data direction register a determine s whether each port a pin is an input or an output. writing a logic 1 to a ddra bit enables t he output buffer for the corresponding port a pin; a logi c 0 disables the output buffer. ddra[7:0] ? data dire ction register a bits these read/write bits control port a data direction. reset clears ddra[7:0], configuring all port a pins as inputs. 1 = corresponding port a pin configured as output 0 = corresponding port a pin configured as input note: avoid glitches on port a pi ns by writing to the port a data register before changing data direction regist er a bits fr om 0 to 1. figure 12-4 shows the port a i/o logic. figure 12-4. port a i/o circuit address: $0004 bit 7654321bit 0 read: ddra7 ddra6 ddra5 ddra4 ddra3 ddra2 ddra1 ddra0 write: reset: 0* 0000000 * ddra7 bit is reset by por or lvi reset only. figure 12-3. data direct ion register a (ddra) read ddra ($0004) write ddra ($0004) reset write pta ($0000) read pta ($0000) ptax ddrax ptax internal data bus f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . input/output ports (i/o) technical data mc68hc908jb8mc68h c08jb8mc68HC08JT8 ? rev. 2.1 204 input/output ports (i/o) motorola when bit ddrax is a l ogic 1, reading address $0000 reads the ptax data latch. when bit ddrax is a logic 0, reading address $0000 reads the voltage level on the pin. the data latch can always be written, regardless of the state of its data direction bit. table 12-2 summarizes the operation of the port a pins. 12.4 port b port b is an 8-bit gener al-purpose bidirectional i/o port with software configurable pullups. 12.4.1 port b data register the port b data register co ntains a data latch for each of the eight port b pins. note: ptb7?ptb0 are not available in the 20-pin pdip, 20-pin soic, and 28-pin soic packages. table 12-2. port a pin functions ddra bit pta bit i/o pin mode accesses to ddra accesses to pta read/write read write 0 x (1) notes: 1. x = don?t care. input, hi-z (2) 2. hi-z = high impedance. ddra[7:0] pin pta[7:0] (3) 3. writing affects data regist er, but does not affect input. 1 x output ddra[7:0] pta[7:0] pta[7:0] address: $0001 bit 7654321bit 0 read: ptb7 ptb6 ptb5 ptb4 ptb3 ptb2 ptb1 ptb0 write: reset: unaffected by reset additional function: optional pullup optional pullup optional pullup optional pullup optional pullup optional pullup optional pullup optional pullup figure 12-5. port b data register (ptb) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . input/output ports (i/o) port b mc68hc908jb8mc68hc08jb8mc68HC08JT8 ? rev. 2.1 technical data motorola input/output ports (i/o) 205 ptb[7:0] ? port b data bits these read/write bits are software-p rogrammable. data direction of each port b pin is under the control of the corresponding bit in data direction register b. reset has no effect on port b data. the port b pullup enable bit, pbp, in the port option control register (pocr) enables pullups on port b pins if t he respective pin is configured as an input. (see 12.8 port options .) 12.4.2 data direction register b data direction register b determine s whether each port b pin is an input or an output. writing a logic 1 to a ddrb bit enables t he output buffer for the corresponding port b pin; a logi c 0 disables the output buffer. ddrb[7:0] ? data dire ction register b bits these read/write bits control port b data direction. reset clears ddrb[7:0], configuring all port b pins as inputs. 1 = corresponding port b pin configured as output 0 = corresponding port b pin configured as input note: avoid glitches on port b pi ns by writing to the port b data register before changing data direction regist er b bits fr om 0 to 1. note: for those devices packaged in a 20-pin pdip, 20-pin soic, and 28-pin soic package, ptb7?ptb0 ar e not connected. ddrb7?ddrb0 should be set to a 1 to conf igure ptb7?ptb0 as outputs. figure 12-7 shows the port b i/o logic. address: $0005 bit 7654321bit 0 read: ddrb7 ddrb6 ddrb5 ddrb4 ddrb3 ddrb2 ddrb1 ddrb0 write: reset: 00000000 figure 12-6. data direct ion register b (ddrb) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . input/output ports (i/o) technical data mc68hc908jb8mc68h c08jb8mc68HC08JT8 ? rev. 2.1 206 input/output ports (i/o) motorola figure 12-7. port b i/o circuit when bit ddrbx is a l ogic 1, reading address $0001 reads the ptbx data latch. when bit ddrbx is a logic 0, reading address $0001 reads the voltage level on the pin. the data latch can always be written, regardless of the state of its data direction bit. table 12-3 summarizes the operation of the port b pins. table 12-3. port b pin functions ddrb bit ptb bit i/o pin mode accesses to ddrb accesses to ptb read/write read write 0 x (1) notes: 1. x = don?t care. input, hi-z (2) 2. hi-z = high impedance. ddrb[7:0] pin ptb[7:0] (3) 3. writing affects data register, but does not affect input. 1 x output ddrb[7:0] ptb[7:0] ptb[7:0] read ddrb ($0005) write ddrb ($0005) reset write ptb ($0001) read ptb ($0001) ptbx ddrbx ptbx internal data bus f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . input/output ports (i/o) port c mc68hc908jb8mc68hc08jb8mc68HC08JT8 ? rev. 2.1 technical data motorola input/output ports (i/o) 207 12.5 port c port c is an 8-bit gener al-purpose bidirectional i/o port with software configurable pullups and current drive options. 12.5.1 port c data register the port c data register c ontains a data latch for each of the eight port c pins. note: ptc7?ptc1 are not available in the 20-pin pdip, 20-pin soic, and 28-pin soic packages. ptc[7:0] ? port c data bits these read/write bits are software-p rogrammable. data direction of each port c pin is under the control of the corresponding bit in data direction register c. reset has no effect on port c data. the port c pullup enable bit, pcp, in the port option control register (pocr) enables pullups on port c pins if the respective pin is configured as an input. (see 12.8 port options .) address: $0002 bit 7654321bit 0 read: ptc7 ptc6 ptc5 ptc4 ptc3 ptc2 ptc1 ptc0 write: reset: unaffected by reset additional function: optional pullup optional pullup optional pullup optional pullup optional pullup optional pullup optional pullup optional pullup figure 12-8. port c data register (ptc) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . input/output ports (i/o) technical data mc68hc908jb8mc68h c08jb8mc68HC08JT8 ? rev. 2.1 208 input/output ports (i/o) motorola 12.5.2 data direction register c data direction register c determines whether eac h port c pin is an input or an output. writing a logic 1 to a ddrc bit enables the output buffer for the corresponding port c pin; a logi c 0 disables the output buffer. ddrc[7:0] ? data dire ction register c bits these read/write bits control port c data direction. reset clears ddrc[7:0], configuring all port c pins as inputs. 1 = corresponding port c pin configured as output 0 = corresponding port c pin configured as input note: avoid glitches on port c pins by writ ing to the port c dat a register before changing data direction regist er c bits fr om 0 to 1. note: for those devices packaged in a 20-pin pdip, 20-pin soic, and 28-pin soic package, ptc7?ptc1 are not connected. ddrc7?ddrc1 should be set to a 1 to conf igure ptc7?ptc1 as outputs. figure 12-10 shows the port c i/o logic. address: $0006 bit 7654321bit 0 read: ddrc7 ddrc6 ddrc5 ddrc4 ddrc3 ddrc2 ddrc1 ddrc0 write: reset: 00000000 figure 12-9. data direct ion register c (ddrc) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . input/output ports (i/o) port d mc68hc908jb8mc68hc08jb8mc68HC08JT8 ? rev. 2.1 technical data motorola input/output ports (i/o) 209 figure 12-10. port c i/o circuit when bit ddrcx is a l ogic 1, reading address $0002 reads the ptcx data latch. when bit ddrcx is a logic 0, reading address $0002 reads the voltage level on the pin. the data latch can always be written, regardless of the state of its data direction bit. table 12-4 summarizes the operation of the port c pins. 12.6 port d port d is an 8-bit gener al-purpose bidirectional i/o port. in 20-pin package, ptd1 and ptd0 internal pads are bonded toget her to ptd0/1 pin. port d pins are open-drain when configured as output, and can interface with 5v logic. table 12-4. port c pin functions ddrc bit ptc bit i/o pin mode accesses to ddrc accesses to ptc read/write read write 0 x (1) notes: 1. x = don?t care. input, hi-z (2) 2. hi-z = high impedance. ddrc[7:0] pin ptc[7:0] (3) 3. writing affects data register, but does not affect input. 1 x output ddrc[7:0] ptc[7:0] ptc[7:0] read ddrc ($0006) write ddrc ($0006) reset write ptc ($0002) read ptc ($0002) ptcx ddrcx ptcx internal data bus f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . input/output ports (i/o) technical data mc68hc908jb8mc68h c08jb8mc68HC08JT8 ? rev. 2.1 210 input/output ports (i/o) motorola 12.6.1 port d data register the port d data register c ontains a data latch for each of the eight port d pins. note: ptd7?ptd2 are not availa ble in the 20-pin pd ip and 20-pin soic packages. ptd7 is not availabl e in the 28-pin soic package. ptd[7:0] ? port d data bits these read/write bits are software programmable. data direction of each port d pin is under control of the corresponding bit in data direction register d. reset has no effect on port d data. the led direct drive bit, ptdldd, in the port opt ion control register (pocr) controls the drive options for the ptd5?ptd2 pins. the infrared led drive bit, ptdildd, in the pocr controls the drive options for the ptd1?ptd0 pins. (see 12.8 port options .) note: in 20-pin package, ptd1 and ptd0 are bonded together to ptd0/1 pin, forming a 50ma high current sink pin. when both ptd1 and ptd0 are configured as output, the values of ptd0 and ptd1 should be written the same. address: $0003 bit 7654321bit 0 read: ptd7 ptd6 ptd5 ptd4 ptd3 ptd2 ptd1 ptd0 write: reset: unaffected by reset additional function: open-drain open-drain open-drain open-drain open-drain open-drain open-drain open-drain 10ma sink 10ma sink 10ma sink 10ma sink 25ma sink 25ma sink figure 12-11. port d da ta register (ptd) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . input/output ports (i/o) port d mc68hc908jb8mc68hc08jb8mc68HC08JT8 ? rev. 2.1 technical data motorola input/output ports (i/o) 211 12.6.2 data direction register d data direction register d determines whether eac h port d pin is an input or an output. writing a logic 1 to a ddrd bit enables the output buffer for the corresponding port d pin; a logi c 0 disables the output buffer. ddrd[7:0] ? data dire ction register d bits these read/write bits control port d data direction. reset clears ddrd[7:0], configuring all port d pins as inputs. 1 = corresponding port d pin configured as output 0 = corresponding port d pin configured as input port d pins are open-drain when configured as output. note: avoid glitches on port d pins by writ ing to the port d dat a register before changing data direction regist er d bits fr om 0 to 1. note: for those devices packaged in a 20-p in pdip and 20-pin soic package, ptd7?ptd2 are not connected. ddrd7?d drd2 should be set to a 1 to configure ptd7?ptd2 as outputs. for those devices packaged in a 28- pin soic package, ptd7 is not connected. ddrd7 should be set to a 1 to configure ptd7 as output. figure 12-13 shows the port d i/o circuit logic. address: $0007 bit 7654321bit 0 read: ddrd7 ddrd6 ddrd5 ddrd4 ddrd3 ddrd2 ddrd1 ddrd0 write: reset: 00000000 figure 12-12. data direct ion register d (ddrd) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . input/output ports (i/o) technical data mc68hc908jb8mc68h c08jb8mc68HC08JT8 ? rev. 2.1 212 input/output ports (i/o) motorola figure 12-13. port d i/o circuit when bit ddrdx is a l ogic 1, reading address $0003 reads the ptdx data latch. when bit ddrdx is a logic 0, reading address $0003 reads the voltage level on the pin. the data latch can always be written, regardless of the state of its data direction bit. table 12-5 summarizes the operation of the port d pins. 12.7 port e port e is a 5-bit special function port th at shares three of its pins with the timer interface module (t im) and two of its pins wi th the usb data pins d+ and d?. pte4 and pte3 are open drain when configured as output. table 12-5. port d pin functions ddrd bit ptd bit i/o pin mode accesses to ddrd accesses to ptd read/write read write 0 x (1) notes: 1. x = don?t care. input, hi-z (2) 2. hi-z = high impedance. ddrd[7:0] pin ptd[7:0] (3) 3. writing affects data register, but does not affect input. 1 x output ddrd[7:0] ptd[7:0] ptd[7:0] read ddrd ($0007) write ddrd ($0007) reset write ptd ($0003) read ptd ($0003) ptdx ddrdx ptdx internal data bus f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . input/output ports (i/o) port e mc68hc908jb8mc68hc08jb8mc68HC08JT8 ? rev. 2.1 technical data motorola input/output ports (i/o) 213 12.7.1 port e data register the port e data register contains a dat a latch for each of the five port e pins. note: pte2 and pte0 are not available in the 20-pin pdi p and 20-pin soic packages. pte[4:0] ? port e data bits pte[4:0] are read/write, software- programmable bits. data direction of each port e pin is under the control of the co rresponding bit in data direction register e. the pte4 and pte3 pullup enable bi ts, pte4p and pte3p, in the port option control regi ster (pocr) enable 5k ? pullups on pte4 and pte3 if the respective pin is configured as an i nput and the usb module is disabled. (see 12.8 port options .) the pte[2:0] pullup enable bit, pt e20p, in the port option control register (pocr) enables pullups on pte2?p te0, regardless of the pin is configured as an i nput or an output. (see 12.8 port options .) address: $0008 bit 7654321bit 0 read: 0 0 0 pte4 pte3 pte2 pte1 pte0 write: reset: unaffected by reset alternative function: d? d+ tch1 tch0 tclk additional function: optional pullup optional pullup optional pullup optional pullup optional pullup additional function: external interrupt open-drain open-drain = unimplemented figure 12-14. port e da ta register (pte) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . input/output ports (i/o) technical data mc68hc908jb8mc68h c08jb8mc68HC08JT8 ? rev. 2.1 214 input/output ports (i/o) motorola pte4 pin functions as an external interrupt when pt e4ie=1 in the irq option control regi ster (iocr) and usben=0 in the usb address register (usb disabled). (see 13.9 irq option control register .) d? and d+ ? usb data pins d? and d+ are the differential data lines used by the usb module. (see section 9. universal se rial bus module (usb) .) the usb module enable bit, usben, in the usb address register (uaddr) controls the pin options for pte4/d ? and pte3/d+. when the usb module is en abled, pte4/d? and pte3/d+ function as usb data pins d? and d+. when the usb module is disabled, pte4/d? and pte3/d+ function as 10ma open-drain pins for ps/2 clock and data use. the pullup enable bit, pull en, in the usb contro l register 3 (ucr3) enables a 1.5k ? pullup on d? pin when t he usb module is enabled. (see 9.8.8 usb control register 3 .) note: pte4/d? pin has two programmable pul lup resistors. one is used for pte4 when the usb module is di sabled and another is used for d? when the usb m odule is enabled. tch1?tch0 ? timer channel i/o bits the pte2/tch1?pte1/tch0 pins ar e the tim input capture/output compare pins. the edge/le vel select bits, elsxb and elsxa, determine whether the pte2/tch 1?pte1/tch0 pins are timer channel i/o pins or general-purpose i/o pins. (see section 11. timer interface module (tim) .) tclk ? timer clock input the pte0/tclk pin is the external clock input fo r the tim. the prescaler select bits, ps[2:0], se lect pte0/tclk as the tim clock input. when not select ed as the tim clock, pt e0/tclk is available for general purpose i/o. (see section 11. timer interface module (tim) .) note: data direction register e (ddre) does not affect the data direction of port e pins that are being used by the tim. however, the ddre bits always determine whether reading port e return s the states of the latches or the states of the pins. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . input/output ports (i/o) port e mc68hc908jb8mc68hc08jb8mc68HC08JT8 ? rev. 2.1 technical data motorola input/output ports (i/o) 215 12.7.2 data direction register e data direction register e determine s whether each port e pin is an input or an output. writing a logic 1 to a ddre bit enables t he output buffer for the corresponding port e pin; a logi c 0 disables the output buffer. ddre[4:0] ? data dire ction register e bits these read/write bits control port e data direction. reset clears ddre[4:0], configuring all port e pins as inputs. 1 = corresponding port e pin configured as output 0 = corresponding port e pin configured as input pte4 and pte3 pins are open-dr ain when configured as output. note: avoid glitches on port e pi ns by writing to the port e data register before changing data direction regist er e bits fr om 0 to 1. note: for those devices packaged in a 20-p in pdip and 20-pin soic package, pte2 and pte0 are not connected. ddre2 and ddre0 should be set to a 1 to configure pte2 and pte0 as outputs. figure 12-16 shows the port e i/o circuit logic. address: $0009 bit 7654321bit 0 read: 0 0 0 ddre4 ddre3 ddre2 ddre1 ddre0 write: reset: 00000000 = unimplemented figure 12-15. data direct ion register e (ddre) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . input/output ports (i/o) technical data mc68hc908jb8mc68h c08jb8mc68HC08JT8 ? rev. 2.1 216 input/output ports (i/o) motorola figure 12-16. port e i/o circuit when bit ddrex is a l ogic 1, reading address $0008 reads the ptex data latch. when bit ddrex is a logic 0, reading address $0008 reads the voltage level on the pin. the data latch can always be written, regardless of the state of its data direction bit. table 12-4 summarizes the operation of the port e pins. 12.8 port options all pins of port a, port b, port c, and port e have programmable pullup resistors. port pins ptd5?ptd0 hav e led drive capability. port pins pte4 and pte3 have 10ma hi gh current driv e capability. table 12-6. port e pin functions ddre bit pte bit i/o pin mode accesses to ddre accesses to pte read/write read write 0 x (1) notes: 1. x = don?t care. input, hi-z (2) 2. hi-z = high impedance. ddre[4:0] pin pte[4:0] (3) 3. writing affects data register, but does not affect input. 1 x output ddre[4:0] pte[4:0] pte[4:0] read ddre ($000c) write ddre ($000c) reset write pte ($0008) read pte ($0008) ptex ddrex ptex internal data bus f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . input/output ports (i/o) port options mc68hc908jb8mc68hc08jb8mc68HC08JT8 ? rev. 2.1 technical data motorola input/output ports (i/o) 217 12.8.1 port option control register the port option control regi ster controls the pullup options for port a, b, c, and e pins. it also controls the drive configur ation on port d. pte20p ? port pte2 ?pte0 pullup enable this read/write bit controls the pu llup option for the pte2?pte0 pins, regardless whether the pins are input or output. 1 = configure pte2?pte0 to have internal pullups to v reg 0 = disconnect pte2?pte0 internal pullups ptdldd ? led direct drive control this read/write bit c ontrols the output cu rrent capability of ptd5?ptd2 pins. when set, each por t pin has 10ma current sink limit. an led can be connected di rectly between the port pin and v dd without the need of a series resistor. 1 = ptd5?ptd2 conf igured for direct led drive capability; when a pin is set as an output, the pin is an o pen-drain pin with 10ma current sink limit 0 = ptd5?ptd2 confi gured as standard open- drain i/o port pin ptdildd ? infrared led drive control this read/write bit controls the output current capability of ptd1 and ptd0 pins. when set, each port pin has 25ma current sink capability. an infrared led can be connected directly between the port pin and v dd . 1 = ptd1 and ptd0 configured fo r infrared led drive capability; when a pin is set as an output, the pin is an o pen-drain pin with 25ma current sink capability 0 = ptd1 and ptd0 configured as standard open-drain i/o port pins address: $001d bit 7654321bit 0 read: pte20p ptdldd ptdildd pte4p pte3p pcp pbp pap write: reset: 00000000 figure 12-17. port option control register (pocr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . input/output ports (i/o) technical data mc68hc908jb8mc68h c08jb8mc68HC08JT8 ? rev. 2.1 218 input/output ports (i/o) motorola pte4p ? pin pte4 pullup enable this read/write bit contro ls the pullup option for the pte4 pin when the pin is configured as an input a nd the usb module is disabled. 1 = configure pte4 to have internal pullup to v dd 0 = disconnect pte4 internal pullup note: when the usb module is enabled, th e pullup controlled by pte4p is disconnected; pte4/d? pin func tions as d? which has a 1.5k ? programmable pull up resistor. (see 9.8.8 usb control register 3 .) pte3p ? pin pte3 pullup enable this read/write bit contro ls the pullup option for the pte3 pin when the pin is configured as an input a nd the usb module is disabled. 1 = configure pte3 to have internal pullup to v dd 0 = disconnect pte3 internal pullup pcp ? port c pullup enable this read/write bit controls the pu llup option for the ptc7?ptc0 pins. when set, a pullup device is connec ted when a pin is configured as an input. 1 = configure port c to have internal pullups to v reg 0 = disconnect port c internal pullups pbp ? port b pullup enable this read/write bit controls the pu llup option for the ptb7?ptb0 pins. when set, a pullup device is connec ted when a pin is configured as an input. 1 = configure port b to have internal pullups to v reg 0 = disconnect port b internal pullups pap ? port a pullup enable this read/write bit controls the pu llup option for the pta7?pta0 pins. when set, a pullup device is connec ted when a pin is configured as an input. 1 = configure port a to have internal pullups to v reg 0 = disconnect port a internal pullups f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc908jb8mc68hc08jb8mc68HC08JT8 ? rev. 2.1 technical data motorola external interrupt (irq) 219 technical data ? mc68hc908jb8?mc68hc08jb8?mc68HC08JT8 section 13. external interrupt (irq) 13.1 contents 13.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 13.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 13.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .220 13.5 irq pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 13.6 pte4/d? pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 13.7 irq module during break interrupts . . . . . . . . . . . . . . . . . . . 223 13.8 irq status and control register . . . . . . . . . . . . . . . . . . . . . . 224 13.9 irq option control regist er. . . . . . . . . . . . . . . . . . . . . . . . . . 225 13.2 introduction the irq module provides tw o external interrupt inputs: one dedicated irq pin and one shared port pin, pte4/d?. 13.3 features features of the irq module include: two external interrupt pins, irq (5v) and pte4/d? (5v) irq interrupt control bits hysteresis buffer programmable edge-only or edge and level interrupt sensitivity automatic interrupt acknowledge low leakage irq pin for external rc wake up input selectable internal pullup resistor f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . external interrupt (irq) technical data mc68hc908jb8mc68h c08jb8mc68HC08JT8 ? rev. 2.1 220 external interrupt (irq) motorola 13.4 functional description a logic 0 applied to the ex ternal interrupt pin ca n latch a cpu interrupt request. figure 13-1 shows the structure of the irq module. interrupt signals on the irq pin are latched into the irq latch. an interrupt latch remains set until on e of the following actions occurs: vector fetch ? a vector fetch au tomatically generates an interrupt acknowledge signal that clears the irq latch. software clear ? software can clea r the interrupt latch by writing to the acknowledge bit in the inte rrupt status and control register (iscr). writing a logi c 1 to the ack bit clears the irq latch. reset ? a reset automatically clears the interrupt latch. the external interrupt pin is fal ling-edge-triggered and is software- configurable to be either falling-edge or low-level-triggered. the mode bit in the iscr controls the tr iggering sensitivity of the irq pin. when the interrupt pin is edge-trigger ed only, the cpu interrupt request remains set until a vector fetch, software clear, or reset occurs. when the interrupt pin is both fallin g-edge and low-leve l-triggered, the cpu interrupt request remains set unt il both of the following occur: vector fetch or software clear return of the interr upt pin to logic one the vector fetch or software clear ma y occur before or af ter the interrupt pin returns to logic 1. as long as the pin is low, t he interrupt request remains pending. a reset will clear the la tch and the mode control bit, thereby clearing the interrup t even if the pin stays low. when set, the imask bi t in the iscr mask all external interrupt requests. a latched interrupt request is not pres ented to the interrupt priority logic unless t he imask bit is clear. note: the interrupt mask (i) in the conditi on code register (ccr) masks all interrupt requests, including ex ternal interrupt requests. (see 8.6 exception control .) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . external interrupt (irq) functional description mc68hc908jb8mc68hc08jb8mc68HC08JT8 ? rev. 2.1 technical data motorola external interrupt (irq) 221 figure 13-1. irq module block diagram addr. register name bit 7 6 5 4 3 2 1 bit 0 $001c irq option control register (iocr) read: 0 0 0 0 0 pte4if pte4ie irqpd write: reset:00000000 $001e irq status and control register (iscr) read: 0 0 0 0 irqf 0 imask mode write: ack reset:00000000 = unimplemented figure 13-2. irq i/o register summary ack imask dq ck clr irq high interrupt to mode select logic irq ff request "1" mode voltage detect synchro- nizer irqf to cpu for bil/bih instructions vector fetch decoder internal address bus reset v dd i nternal pullup device dq ck clr "1" pte4if pte4ie pte4 irq irqpd read iocr to pte4 pullup enable circuitry f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . external interrupt (irq) technical data mc68hc908jb8mc68h c08jb8mc68HC08JT8 ? rev. 2.1 222 external interrupt (irq) motorola 13.5 irq pin the irq pin has a low leakage for input voltages ranging from 0v to v dd ; suitable for applications using rc discharge circuitry to wake up the mcu. a logic 0 on the irq pin can latch an interrupt request into the irq latch. a vector fetch, software clear , or reset clears the irq latch. if the mode bit is set, the irq pin is both falling- edge-sensitive and low- level-sensitive. with mode set, both of the following actions must occur to clear irq: vector fetch or software clear ? a vector fetc h generates an interrupt acknowledge signal to cl ear the latch. software may generate the interrupt acknowledge si gnal by writing a logic 1 to the ack bit in the inte rrupt status and contro l register (iscr). the ack bit is useful in applic ations that poll the irq pin and require software to clear the irq latch. writing to the ac k bit prior to leaving an interrupt service rout ine can also prevent spurious interrupts due to noise. setting ack does not af fect subsequent transitions on the irq pin. a falling edge that occurs after writing to the ack bi t latches another interrupt request. if t he irq mask bit, imask, is clear, the cpu loads the progr am counter with the vector address at lo cations $fff 8 and $fff9. return of the irq pin to logic one ? as long as the irq pin is at logic zero, irq remains active. the vector fetch or software cl ear and the return of the irq pin to logic one may occur in any or der. the interrupt reques t remains pending as long as the irq pin is at logic zero. a rese t will clear the latch and the mode control bit, thereby clearing the interrupt ev en if the pin stays low. if the mode bit is clear, the irq pin is falling-edge- sensitive only. with mode clear, a vector fetc h or software clear im mediately clears the irq latch. the irqf bit in the i scr register can be us ed to check for pending interrupts. the irqf bit is not affect ed by the imask bit, which makes it useful in applications wh ere polling is preferred. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . external interrupt (irq) pte4/d? pin mc68hc908jb8mc68hc08jb8mc68HC08JT8 ? rev. 2.1 technical data motorola external interrupt (irq) 223 use the bih or bil in struction to read the logic level on the irq pin. note: when using the level-sensit ive interrupt trigger, av oid false interrupts by masking interrupt requests in the interrupt routine. note: an internal pullup resistor to v dd is connected to irq pin; this can be disabled by setting the irqpd bit in the irq option control register ($001c). 13.6 pte4/d? pin the pte4 pin is configured as an in terrupt input to trigger the irq interrupt when the followi ng conditions ar e satisfied: the usb module is di sabled (usben = 0) pte4 pin configured for external interrupt input (pte4ie = 1) setting pte4ie configures the pte4 pi n to an input pin with an internal pullup device. the pte4 interrup t is "ored" with the irq input to trigger the irq interrupt (see figure 13-1 . irq m odule block diagram ). therefore, the irq status and contro l register affects both the irq pin and the pte pin. an interrupt on pte4 also sets the pte4 interrupt flag, pte4if, in the irq option control register (iocr). 13.7 irq module during break interrupts the system integration module (sim) co ntrols whether the irq latch can be cleared during the break state. the bcfe bit in the break flag control register (bfcr) enables software to clear the latches during the break state. (see section 8. system in tegration module (sim) .) to allow software to clear the irq la tch during a break interrupt, write a logic 1 to the bcfe bit. if a latch is cleared dur ing the break state, it remains cleared when the m cu exits the break state. to protect the latches during the break state, write a logic 0 to the bcfe bit. with bcfe at logic 0 (its default state), writi ng to the ack bit in the irq status and control regi ster during the break state has no effect on the irq latch. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . external interrupt (irq) technical data mc68hc908jb8mc68h c08jb8mc68HC08JT8 ? rev. 2.1 224 external interrupt (irq) motorola 13.8 irq status and control register the irq status and control register (iscr) controls and monitors operation of the irq m odule. the iscr has the following functions: shows the state of the irq flag clears the irq latch masks irq interrupt request controls triggering se nsitivity of the irq pin irqf ? irq flag this read-only status bi t is high when the irq interrupt is pending. 1 = irq interrupt pending 0 = irq interr upt not pending ack ? irq interrupt request acknowledge bit writing a logic 1 to this write-only bit clears the irq latch. ack always reads as logic 0. reset clears ack. imask ? irq interrupt mask bit writing a logic 1 to this read/write bit disables irq interrupt requests. reset clears imask. 1 = irq interrupt requests disabled 0 = irq interrupt requests enabled mode ? irq edge/lev el select bit this read/write bit cont rols the triggering se nsitivity of the irq pin. reset clears mode. 1 = irq interrupt requests on fa lling edges and low levels 0 = irq interrupt requests on falling edges only address: $001e bit 7654321bit 0 read: 0000irqf0 imask mode write: ack reset: 00000000 = unimplemented figure 13-3. irq status and control register (iscr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . external interrupt (irq) irq option control register mc68hc908jb8mc68hc08jb8mc68HC08JT8 ? rev. 2.1 technical data motorola external interrupt (irq) 225 13.9 irq option control register the irq option control r egister controls and mo nitors the external interrupt function availabl e on the pte4 pin. it al so disables/enables the pullup resistor on the irq pin. controls pullup option on irq pin enables pte4 pin for exte rnal interrupts to irq shows the state of t he pte4 interrupt flag pte4if ? pte4 interrupt flag this read-only status bi t is high when a falli ng edge on pte4 pin is detected. pte4if bit clear s when the iocr is read. 1 = falling edge on pte4 is detected and pte4ie is set 0 = falling edge on pte4 is not detected or pte4ie is clear pte4ie ? pte4 interrupt enable this read/write bit enables or disables the in terrupt function on the pte4 pin to trigger the irq inte rrupt. setting the pte4ie bit and clearing the usben bit in the usb address regi ster configure the pte4 pin for interrupt function to the irq interrupt. setting pte4ie also enables the inter nal pullup on pte4 pin. 1 = pte4 interrupt enabled; triggers irq interrupt 0 = pte4 interrupt disabled irqpd ? irq pullup disable this read/write bit c ontrols the pullup option for the irq pin. 1 = internal pull up is disconnected 0 = internal pull-up is connec ted between irq pin and v dd address: $001c bit 7654321bit 0 read: 00000pte4if pte4ie irqpd write: reset: 00000000 = unimplemented figure 13-4. irq option control register (iocr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . external interrupt (irq) technical data mc68hc908jb8mc68h c08jb8mc68HC08JT8 ? rev. 2.1 226 external interrupt (irq) motorola f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc908jb8mc68hc08jb8mc68HC08JT8 ? rev. 2.1 technical data motorola keyboard interrupt module (kbi) 227 technical data ? mc68hc908jb8?mc68hc08jb8?mc68HC08JT8 section 14. keyboard interrupt module (kbi) 14.1 contents 14.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 14.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 14.4 pin name conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 14.5 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .230 14.6 keyboard initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 14.7 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 14.7.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .232 14.7.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .232 14.8 keyboard module during break interrupts . . . . . . . . . . . . . . . 233 14.9 i/o registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 14.9.1 keyboard status and control register. . . . . . . . . . . . . . . . 233 14.9.2 keyboard interrupt enable register . . . . . . . . . . . . . . . . . . 235 14.2 introduction the keyboard interrupt module (kbi ) provides eight independently maskable external interrupts whic h are accessible via pta0?pta7 pins. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . keyboard interrupt module (kbi) technical data mc68hc908jb8mc68h c08jb8mc68HC08JT8 ? rev. 2.1 228 keyboard interrupt module (kbi) motorola 14.3 features features of the keyboard interrupt module include: eight keyboard interrupt pins with separate keyboard interrupt enable bits and one keyb oard interrupt mask hysteresis buffers programmable edge-only or edge- and level-interrupt sensitivity exit from low-power modes 14.4 pin name conventions the kbi share eight i/o pins with eight port a i/o pins. the full name of the i/o pins are listed in table 14-1 . the generic pin name appear in the text that follows. table 14-1. kbi pi n name conventions full kbi pin names: kbi generic pin names: pta7/kba7 kba7 pta7/kba6 kba6 pta7/kba5 kba5 pta7/kba4 kba4 pta7/kba3 kba3 pta7/kba2 kba2 pta7/kba1 kba1 pta7/kba0 kba0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . keyboard interrupt module (kbi) pin name conventions mc68hc908jb8mc68hc08jb8mc68HC08JT8 ? rev. 2.1 technical data motorola keyboard interrupt module (kbi) 229 figure 14-1. keyboard module block diagram kbie0 kbie7 . . . dq ck clr v reg modek imaskk keyboard interrupt ff vector fetch decoder ackk internal bus reset kba7 kba0 synchronizer keyf keyboard interrupt request to pullup enable to pullup enable table 14-2. i/o register summary addr.register name bit 7654321bit 0 $0016 keyboard status and control register (kbscr) read: 0 0 0 0 keyf 0 imaskk modek write: ackk reset:00000000 $0017 keyboard interrupt enable register (kbier) read: kbie7 kbie6 kbie5 kbie4 kbie3 kbie2 kbie1 kbie0 write: reset:00000000 = unimplemented f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . keyboard interrupt module (kbi) technical data mc68hc908jb8mc68h c08jb8mc68HC08JT8 ? rev. 2.1 230 keyboard interrupt module (kbi) motorola 14.5 functional description writing to the kbie7?kbie0 bits in the keyboard interrupt enable register independently enables or disables each port a pin as a keyboard interrupt pin. enabling a keyboard interrupt pin al so enables its internal pullup device. a logic 0 applied to an enabled keyboar d interrupt pin latches a keyboard interrupt request. a keyboard interrupt is latched w hen one or more keyboard pins goes low after all were high. the modek bit in the keyboard status and control register controls the triggering mode of the keyboard interrupt. if the keyboard interrupt is e dge-sensitive only, a falling edge on a keyboard pin does not latch an in terrupt reques t if another keyboard pin is already low. if the keyboard interrupt is falli ng edge- and low level-sensitive, an interrupt request is present as long as any keyboard pin is low. note: to prevent losing an interrupt reques t on one pin because another pin is still low, software can disable the latter pin while it is low. if the modek bit is set, the keyboard interrupt pins ar e both falling edge- and low level-sensitive, and both of t he following actions must occur to clear a keyboard interrupt request: vector fetch or software clear ? a vector fetc h generates an interrupt acknowledge signal to clear the interrupt request. software may generate the inte rrupt acknowle dge signal by writing a logic 1 to t he ackk bit in the keyboa rd status and control register (kbscr). the a ckk bit is useful in applications that poll the keyboard interrupt pins and require software to clear the keyboard interrupt request. writing to the ackk bit prior to leaving an interrupt service routine also can prevent spurious interrupts due to noise. setting ackk does not affect subsequent transitions on the keyboard interrupt pins. a falling edge that occurs after writing to the ackk bi t latches another inte rrupt request. if the keyboard interrupt mask bit, imask k, is clear, the cpu loads the program counter with the vect or address at locations $fff0 and $fff1. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . keyboard interrupt module (kbi) keyboard initialization mc68hc908jb8mc68hc08jb8mc68HC08JT8 ? rev. 2.1 technical data motorola keyboard interrupt module (kbi) 231 return of all enabled keyboard interr upt pins to logic 1 ? as long as any enabled keyboard interrupt pin is at logic 0, the keyboard interrupt remains set. the vector fetch or software clear and the return of all enabled keyboard interrupt pins to logic 1 may occur in any order. if the modek bit is clear, the key board interrupt pin is falling-edge- sensitive only. with mo dek clear, a vector fetc h or software clear immediately clears the ke yboard interrupt request. reset clears the keyboard interrupt request and the modek bit, clearing the interrupt request even if a keyboard interrupt pin stays at logic 0. the keyboard flag bit (keyf) in the ke yboard status and control register can be used to see if a pending inte rrupt exists. the keyf bit is not affected by the keyboard interrupt mask bit (imaskk) which makes it useful in applications wh ere polling is preferred. to determine the logi c level on a keyboard inte rrupt pin, use the data direction register to configure the pin as an input and read the data register. note: setting a keyboard interrupt enable bi t (kbiex) forces the corresponding keyboard interrupt pin to be an inpu t, overriding t he data direction register. however, the dat a direction register bi t must be a logic 0 for software to read the pin. 14.6 keyboard initialization when a keyboard interrupt pin is enab led, it takes time for the pullup device to reach a logic 1. therefore, a false interrupt can occur as soon as the pin is enabled. to prevent a false interrupt on keyboard initialization: 1. mask keyboard interrupts by se tting the imaskk bit in the keyboard status and control register. 2. enable the kbi pins by setting the appropriate kbiex bits in the keyboard interrupt enable register. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . keyboard interrupt module (kbi) technical data mc68hc908jb8mc68h c08jb8mc68HC08JT8 ? rev. 2.1 232 keyboard interrupt module (kbi) motorola 3. write to the ackk bit in the keyboard status and control register to clear any false interrupts. 4. clear the imaskk bit. an interrupt signal on an edg e-triggered pin can be acknowledged immediately after enabling the pin. an interrupt si gnal on an edge- and level-triggered interrupt pin must be acknowledged afte r a delay that depends on the external load. another way to avoi d a false interrupt: 1. configure the keyboard pins as outputs by setting the appropriate ddra bits in data di rection register a. 2. write logic 1s to the appropriate port a data register bits. 3. enable the kbi pins by setting the appropriate kbiex bits in the keyboard interrupt enable register. 14.7 low-power modes the wait and stop in structions put the mcu in low-power consumption standby modes. 14.7.1 wait mode the keyboard module remains active in wait mode. clearing the imaskk bit in the keyboar d status and control r egister enables keyboard interrupt requests to brin g the mcu out of wait mode. 14.7.2 stop mode the keyboard module remains active in stop mode. clearing the imaskk bit in the keyboar d status and control r egister enables keyboard interrupt requests to bring the mcu out of stop mode. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . keyboard interrupt module (kbi) keyboard module during break interrupts mc68hc908jb8mc68hc08jb8mc68HC08JT8 ? rev. 2.1 technical data motorola keyboard interrupt module (kbi) 233 14.8 keyboard module during break interrupts the system integration module (sim) controls whether the keyboard interrupt latch can be cleared during t he break state. the bcfe bit in the break flag control register (bfcr) enabl es software to clear status bits during the break state. to allow software to clear the key board interrupt la tch during a break interrupt, write a logic 1 to the bcfe bit. if a latch is cleared during the break state, it remains cleared w hen the mcu exits the break state. to protect the latch during the break st ate, write a logi c 0 to the bcfe bit. with bcfe at logi c 0 (its default state), writing to the keyboard acknowledge bit (ackk) in the keyboard status and control register during the break stat e has no effect. (see 14.9.1 keyboard status and control register .) 14.9 i/o registers these registers control a nd monitor operation of the keyboard module: keyboard status and cont rol register (kbscr) keyboard interrupt enabl e register (kbier) 14.9.1 keyboard status and control register the keyboard status and control register: flags keyboard interrupt requests acknowledges keyboard interrupt requests masks keyboard interrupt requests controls keyboard interrupt triggering sensitivity f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . keyboard interrupt module (kbi) technical data mc68hc908jb8mc68h c08jb8mc68HC08JT8 ? rev. 2.1 234 keyboard interrupt module (kbi) motorola bits 7?4 ? not used these read-only bits alwa ys read as logic 0s. keyf ? keyboard flag bit this read-only bit is set when a ke yboard interrupt is pending. reset clears the keyf bit. 1 = keyboard interrupt pending 0 = no keyboard interrupt pending ackk ? keyboard acknowledge bit writing a logic 1 to th is write-only bit clears the keyboard interrupt request. ackk always reads as logic 0. rese t clears ackk. imaskk ? keyboard interrupt mask bit writing a logic 1 to th is read/write bit prev ents the output of the keyboard interrupt mask from gene rating interrupt requests. reset clears the imaskk bit. 1 = keyboard interrupt requests masked 0 = keyboard interrupt requests not masked modek ? keyboard tri ggering sensitivity bit this read/write bit controls the tri ggering sensitivity of the keyboard interrupt pins. reset clears modek. 1 = keyboard interrupt reques ts on falling edges and low levels 0 = keyboard interrupt requests on falling edges only address: $0016 bit 7654321bit 0 read: 0000 keyf 0 imaskk modek write: ackk reset:00000000 = unimplemented figure 14-2. keyboard status and control regi ster (kbscr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . keyboard interrupt module (kbi) i/o registers mc68hc908jb8mc68hc08jb8mc68HC08JT8 ? rev. 2.1 technical data motorola keyboard interrupt module (kbi) 235 14.9.2 keyboard interrupt enable register the keyboard interrupt enabl e register enables or disables each port a pin to operate as a ke yboard interrupt pin. kbie7?kbie0 ? keyboard interrupt enable bits each of these read/write bits enables the corres ponding keyboard interrupt pin to latch interrupt requests. reset clears the keyboard interrupt enable register. 1 = ptax pin enabled as keyboard interrupt pin 0 = ptax pin not enabled as keyboard interrupt pin address: $0017 bit 7654321bit 0 read: kbie7 kbie6 kbie5 kbie4 kbie3 kbie2 kbie1 kbie0 write: reset:00000000 figure 14-3. keyboard interr upt enable register (kbier) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . keyboard interrupt module (kbi) technical data mc68hc908jb8mc68h c08jb8mc68HC08JT8 ? rev. 2.1 236 keyboard interrupt module (kbi) motorola f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc908jb8mc68hc08jb8mc68HC08JT8 ? rev. 2.1 technical data motorola computer operating properly (cop) 237 technical data ? mc68hc908jb8?mc68hc08jb8?mc68HC08JT8 section 15. computer operating properly (cop) 15.1 contents 15.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 15.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .238 15.4 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 15.4.1 oscxclk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .239 15.4.2 stop instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 15.4.3 copctl write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .239 15.4.4 power-on reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 15.4.5 internal reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 15.4.6 reset vector fetch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 15.4.7 copd (cop disable). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 15.4.8 coprs (cop rate sele ct) . . . . . . . . . . . . . . . . . . . . . . . . 240 15.5 cop control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 15.6 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .241 15.7 monitor mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .241 15.8 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 15.8.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .242 15.8.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .242 15.9 cop module during break mode . . . . . . . . . . . . . . . . . . . . . . 242 15.2 introduction the computer operating properly (cop ) module contains a free-running counter that generates a reset if allowed to overflow. the cop module helps software recover from runa way code. prevent a cop reset by clearing the cop counter periodically. the cop module can be disabled through the copd bit in the config register. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . computer operating properly (cop) technical data mc68hc908jb8mc68h c08jb8mc68HC08JT8 ? rev. 2.1 238 computer operating properly (cop) motorola 15.3 functional description figure 15-1 shows the structure of the cop module. figure 15-1. cop block diagram the cop counter is a free-running 6- bit counter preceded by a 12-bit system integration module (sim) counter. if not cl eared by software, the cop counter overflows and generates an asynchronous reset after 2 18 ?2 4 or 2 13 ?2 4 oscxclk cycles, depending on the state of the cop rate select bit, coprs in t he configuration register. with a 2 18 ?2 4 oscxclk cycle overflow option (c oprs = 0), a 12mhz oscxclk clock (6mhz crystal) gives a cop ti meout period of 21.84 ms. writing any value to location $ffff before an overflow occurs prevents a cop reset by clearing the cop counter and stages 12 through 5 of the sim counter. copctl write oscxclk reset vector fetch sim reset circuit reset status register internal reset sources (1) sim clear stages 5?12 12-bit sim counter clear all stages copd (from config) reset copctl write clear cop module copen (from sim) cop counter note: 1. see sim section for more details. cop clock cop timeout cop rate sel (coprs from config) 6-bit cop counter f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . computer operating properly (cop) i/o signals mc68hc908jb8mc68hc08jb8mc68HC08JT8 ? rev. 2.1 technical data motorola computer operating properly (cop) 239 note: service the cop immediately after re set and before entering or after exiting stop mode to guarantee the ma ximum time before the first cop counter overflow. a cop reset pulls the rst pin low for 32 oscxcl k cycles and sets the cop bit in the reset st atus register (rsr). in monitor mode, the cop is disabled if the rst pin or the irq is held at v dd + v hi . during the break state, v dd + v hi on the rst pin disables the cop. note: place cop clearing instructions in the main program and not in an interrupt subroutine. su ch an interrupt subrout ine could keep the cop from generating a reset even while the main pr ogram is not working properly. 15.4 i/o signals the following paragraphs descri be the signals shown in figure 15-1 . 15.4.1 oscxclk oscxclk is the clock doubler output signal. oscxclk frequency is double of the cr ystal frequency. 15.4.2 stop instruction the stop instruction cl ears the cop prescaler. 15.4.3 copctl write writing any value to the cop c ontrol register (copctl) (see 15.5 cop control register ) clears the cop counter a nd clears bits 12 through 5 of the sim counter. readi ng the cop control register returns the low byte of the reset vector. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . computer operating properly (cop) technical data mc68hc908jb8mc68h c08jb8mc68HC08JT8 ? rev. 2.1 240 computer operating properly (cop) motorola 15.4.4 power-on reset the power-on reset (por) circuit in the sim clears the cop prescaler 4096 oscxclk cycles after power-up. 15.4.5 internal reset an internal reset clears the sim counter and the cop counter. 15.4.6 reset vector fetch a reset vector fetch occurs when the vector addres s appears on the data bus. a reset vector fetch clears the cop prescaler. 15.4.7 copd (cop disable) the copd signal reflec ts the state of the cop di sable bit (copd) in the configuration regi ster (config). 15.4.8 coprs (cop rate select) the coprs signal reflects the state of the cop ra te select bit (coprs) in the configuration register (config). address: $001f bit 7654321bit 0 read: 0 0 urstd lvid ssrec coprs stop copd write: reset:00000000 = unimplemented figure 15-2. configura tion register (config) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . computer operating properly (cop) cop control register mc68hc908jb8mc68hc08jb8mc68HC08JT8 ? rev. 2.1 technical data motorola computer operating properly (cop) 241 coprs ? cop rate select bit coprs selects the cop timeout period. rese t clears coprs. 1 = cop timeout period is (2 13 ? 2 4 ) oscxout cycles 0 = cop timeout period is (2 18 ? 2 4 ) oscxout cycles copd ? cop disable bit copd disables the cop module. 1 = cop module disabled 0 = cop module enabled 15.5 cop control register the cop control register is locat ed at address $ffff and overlaps the reset vector. writing any value to $ffff clears t he cop counter and starts a new timeout per iod. reading location $ffff returns the low byte of the reset vector. 15.6 interrupts the cop does not generate cpu interrupt requests. 15.7 monitor mode the cop is disabled in monitor mode when v dd + v hi is present on the irq pin or on the rst pin. address: $ffff bit 7654321bit 0 read: low byte of reset vector write: clear cop counter reset: unaffected by reset figure 15-3. cop contro l register (copctl) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . computer operating properly (cop) technical data mc68hc908jb8mc68h c08jb8mc68HC08JT8 ? rev. 2.1 242 computer operating properly (cop) motorola 15.8 low-power modes the wait and stop in structions put the mcu in low-power consumption standby modes. 15.8.1 wait mode the cop remains active during wait mode. to prevent a cop reset during wait mode, periodi cally clear the cop counter in a cpu interrupt routine. 15.8.2 stop mode stop mode turns off the oscxclk input to the cop and clears the cop prescaler. service the co p immediately before ent ering or after exiting stop mode to ensure a full cop timeout period a fter entering or exiting stop mode. the stop bit in the configuration r egister (config) enables the stop instruction. to prevent inadvertently turning of f the cop with a stop instruction, disable th e stop instruction by clearing the stop bit. 15.9 cop module during break mode the cop is disabled during a break interrupt when v dd + v hi is present on the rst pin. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc908jb8mc68hc08jb8mc68HC08JT8 ? rev. 2.1 technical data motorola low voltage inhibit (lvi) 243 technical data ? mc68hc908jb8?mc68hc08jb8?mc68HC08JT8 section 16. low voltage inhibit (lvi) 16.1 contents 16.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 16.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .243 16.4 lvi control register (config) . . . . . . . . . . . . . . . . . . . . . . .244 16.5 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 16.5.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .244 16.5.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .244 16.2 introduction this section describes the low-vo ltage inhibit module (lvi), which monitors the vo ltage on the v dd pin and generates a reset when the v dd voltage falls to the lvi trip (v lvr ) voltage. 16.3 functional description figure 16-1 shows the structur e of the lvi module. the lvi is enabled after a reset. the lvi module cont ains a bandgap refe rence circuit and comparator. setting lvi di sable bit (lvid) disables the lvi to monitor v dd voltage. the lvi module generates one output signal: lvi reset ? an reset signal w ill be generated to reset the cpu when v dd drops to below t he set trip point. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . low voltage inhibit (lvi) technical data mc68hc908jb8mc68h c08jb8mc68HC08JT8 ? rev. 2.1 244 low voltage inhibit (lvi) motorola figure 16-1. lvi module block diagram 16.4 lvi control register (config) lvid ?tlow voltage inhibit disable bit 1 = low voltage inhibit disabled 0 = low voltage inhibit enabled 16.5 low-power modes the stop and wait instructions put the mcu in low-power consumption standby modes. 16.5.1 wait mode the lvi module, when enabl ed, will continue to op erate in wait mode. 16.5.2 stop mode the lvi module, when enabl ed, will continue to op erate in stop mode. low v dd lv i d detector v dd lvi reset v dd > v lvr = 0 v dd < v lvr = 1 address: $001f bit 7654321bit 0 read: 0 0 urstd lvid ssrec coprs stop copd write: reset:00000000 one-time writable register after each reset. urstd and lvid bits are reset by por or lvi reset only. = unimplemented figure 16-2. configurat ion register (config) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc908jb8mc68hc08jb8mc68HC08JT8 ? rev. 2.1 technical data motorola break module (break) 245 technical data ? mc68hc908jb8?mc68hc08jb8?mc68HC08JT8 section 17. break module (break) 17.1 contents 17.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 17.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246 17.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .246 17.4.1 flag protection during break interr upts . . . . . . . . . . . . . . . 248 17.4.2 cpu during break interrupts . . . . . . . . . . . . . . . . . . . . . . .248 17.4.3 tim during break interr upts . . . . . . . . . . . . . . . . . . . . . . . . 248 17.4.4 cop during break interrupts . . . . . . . . . . . . . . . . . . . . . . . 248 17.5 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 17.5.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .248 17.5.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .249 17.6 break module registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 17.6.1 break status and control register. . . . . . . . . . . . . . . . . . . 249 17.6.2 break address register s . . . . . . . . . . . . . . . . . . . . . . . . . . 250 17.6.3 break status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 17.6.4 break flag control register (bfcr) . . . . . . . . . . . . . . . . . 252 17.2 introduction this section describes the break module. the break module can generate a break interrupt that stops normal program flow at a defined address to enter a background program. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . break module (break) technical data mc68hc908jb8mc68h c08jb8mc68HC08JT8 ? rev. 2.1 246 break module (break) motorola 17.3 features features of the break m odule include the following: accessible i/o registers during the break interrupt cpu-generated break interrupts software-generated break interrupts cop disabling during break interrupts 17.4 functional description when the internal address bus matches the value written in the break address registers, the br eak module issues a breakpoint signal (bkpt ) to the sim. the sim then causes the cpu to load t he instruction register with a software interrupt instruction (swi) after completi on of the current cpu instruction. the program coun ter vectors to $fffc and $fffd ($fefc and $fefd in monitor mode). these events can cause a br eak interrupt to occur: a cpu-generated address (the addr ess in the program counter) matches the contents of th e break address registers. software writes a logic 1 to the brka bit in the break status and control register. when a cpu-generated addre ss matches the contents of the break address registers, th e break interrupt begins af ter the cpu completes its current instruction. a return-from-inter rupt instruction (r ti) in the break routine ends the break interrupt and returns the mcu to normal operation. figure 17-1 shows the structure of the break module. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . break module (break) functional description mc68hc908jb8mc68hc08jb8mc68HC08JT8 ? rev. 2.1 technical data motorola break module (break) 247 figure 17-1. break module block diagram iab[15:8] iab[7:0] 8-bit comparator 8-bit comparator control break address register low break address register high iab[15:0] bkpt (to sim) addr.register name bit 7654321bit 0 $fe00 break status register (bsr) read: rrrrrr sbsw r write: see note reset: 0 $fe03 break flag control register (bfcr) read: bcferrrrrrr write: reset: 0 $fe0c break address high register (brkh) read: bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 write: reset:00000000 $fe0d break address low register (brkl) read: bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 write: reset:00000000 $fe0e break status and control register (brkscr) read: brke brka 000000 write: reset:00000000 note: writing a logic 0 clears sbsw. = unimplemented r = reserved figure 17-2. break i/ o register summary f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . break module (break) technical data mc68hc908jb8mc68h c08jb8mc68HC08JT8 ? rev. 2.1 248 break module (break) motorola 17.4.1 flag protection during break interrupts the bcfe bit in the break flag control register (bfcr) enables software to clear status bits during the break state. 17.4.2 cpu during break interrupts the cpu starts a br eak interrupt by: loading the instruction regist er with the swi instruction loading the program counter with $fffc and $fffd ($fefc and $fefd in monitor mode) the break interrupt begins after completion of t he cpu instruction in progress. if the break address register match occurs on the last cycle of a cpu instruction, the break interrupt begins immediately. 17.4.3 tim during break interrupts a break interrupt stops the timer counter. 17.4.4 cop during break interrupts the cop is disabled during a break interrupt when v reg +v hi is present on the rst pin. 17.5 low-power modes the wait and stop in structions put the mcu in low-power- consumption standby modes. 17.5.1 wait mode if enabled, the break module is active in wait mode. in the break routine, the user can subtract one from the re turn address on the stack if sbsw is set (see 8.7 low-power modes ). clear the sbsw bi t by writing logic 0 to it. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . break module (break) break module registers mc68hc908jb8mc68hc08jb8mc68HC08JT8 ? rev. 2.1 technical data motorola break module (break) 249 17.5.2 stop mode a break interrupt causes exit from stop mode and sets the sbsw bit in the break status register. see 8.8 sim registers . 17.6 break module registers these registers cont rol and monitor operation of the break module: break status and cont rol register (brkscr) break address regi ster high (brkh) break address regi ster low (brkl) break status register (bsr) break flag contro l register (bfcr) 17.6.1 break status and control register the break status and control register contains break module enable and status bits. brke ? break enable bit this read/write bit enabl es breaks on break address register matches. clear brke by writing a logic 0 to bit 7. reset clears the brke bit. 1 = breaks enabled on 16-bit address match 0 = breaks disabled address: $fe0e bit 7654321bit 0 read: brke brka 000000 write: reset: 00000000 = unimplemented figure 17-3. break status an d control register (brkscr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . break module (break) technical data mc68hc908jb8mc68h c08jb8mc68HC08JT8 ? rev. 2.1 250 break module (break) motorola brka ? break active bit this read/write status and control bit is se t when a break address match occurs. writing a logic 1 to brka generates a br eak interrupt. clear brka by writing a l ogic 0 to it before exit ing the break routine. reset clears the brka bit. 1 = break address match 0 = no break address match 17.6.2 break address registers the break address registers contai n the high and low bytes of the desired breakpoint address. reset cl ears the break ad dress registers. 17.6.3 break status register the break status regi ster (bsr) contains a flag to indicate that a break caused an exit from stop or wait mode. this stat us bit is useful in applications requiring a re turn to wait or stop m ode after exiting from a break interrupt. address: $fe0c bit 7654321bit 0 read: bit 15 14 13 12 11 10 9 bit 8 write: reset:00000000 figure 17-4. break addres s register high (brkh) address: $fe0d bit 7654321bit 0 read: bit 7654321bit 0 write: reset:00000000 figure 17-5. break addr ess register low (brkl) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . break module (break) break module registers mc68hc908jb8mc68hc08jb8mc68HC08JT8 ? rev. 2.1 technical data motorola break module (break) 251 sbsw ? sim break stop/wait this read/write bit is se t when a break interrupt causes an exit from wait or stop mode. clear sbsw by writing a logi c 0 to it. reset clears sbsw. 1 = stop mode or wa it mode was exited by break interrupt 0 = stop mode or wait mode was not exited by break interrupt sbsw can be read within the break state swi r outine. the user can modify the return address on the st ack by subtractin g one from it. the following code is an example of this. this code works if the h register was stacked in the break interrupt routine. execute this code at the end of the break interrupt routine. address: $fe00 bit 7654321bit 0 read: rrrrrr sbsw r write: note (1) reset: 0 r = reserved 1. writing a logic zero clears sbsw. figure 17-6. break stat us register (bsr) hibyte equ 5 lobyte equ 6 ; if not sbsw, do rti brclr sbsw,bsr, return ; ; see if wait mode or stop mode was exited by break. tst lobyte,sp ; if returnlo is not zero, bne dolo ; then just decrement low byte. dec hibyte,sp ; else deal with high byte, too. dolo dec lobyte,sp ; point to wait/stop opcode. return pulh rti ; restore h register. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . break module (break) technical data mc68hc908jb8mc68h c08jb8mc68HC08JT8 ? rev. 2.1 252 break module (break) motorola 17.6.4 break flag control register (bfcr) the break control register contains a bit that enables so ftware to clear status bits while the mc u is in a break state. bcfe ? break clear flag enable bit this read/write bit enables software to clear st atus bits by accessing status registers while the mcu is in a break state. to clear status bits during the break state, t he bcfe bit must be set. 1 = status bits clearable during break 0 = status bits not clearable during break address: $fe03 bit 7654321bit 0 read: bcferrrrrrr write: reset: 0 r=reserved figure 17-7. brea k flag control regi ster high (bfcr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc908jb8mc68hc08jb8mc68HC08JT8 ? rev. 2.1 technical data motorola electrical specifications 253 technical data ? mc68hc908jb8?mc68hc08jb8?mc68HC08JT8 section 18. electrical specifications 18.1 contents 18.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253 18.3 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . 254 18.4 functional operating range. . . . . . . . . . . . . . . . . . . . . . . . . . 255 18.5 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255 18.6 dc electrical characterist ics . . . . . . . . . . . . . . . . . . . . . . . . . 256 18.7 control timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257 18.8 oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257 18.9 usb dc electrical charac teristics . . . . . . . . . . . . . . . . . . . . . 258 18.10 usb low-speed source electrical characteri stics . . . . . . . . 259 18.11 usb signaling levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260 18.12 timer interface module characterist ics . . . . . . . . . . . . . . . . . 260 18.13 memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 18.2 introduction this section contains electrical and timing specifications. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . electrical specifications technical data mc68hc908jb8mc68h c08jb8mc68HC08JT8 ? rev. 2.1 254 electrical specifications motorola 18.3 absolute maximum ratings maximum ratings are t he extreme limits to which the mcu can be exposed without perman ently damaging it. note: this device is not guar anteed to operate properly at the maximum ratings. refer to 18.6 dc electrical characteristics for guaranteed operating conditions. note: this device contains circ uitry to protect the i nputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid applic ation of any voltage higher than maximum-rated voltages to this hi gh-impedance circui t. for proper operation, it is recommended that v in and v out be constrained to the range v ss (v in or v out ) v reg . reliability of operation is enhanced if unused inputs are connected to an appr opriate logic voltage level (for example, either v ss or v reg ). characteristic (1) notes: 1. voltages referenced to v ss symbol value unit supply voltage v dd ?0.3 to +6.0 v input voltage pte4/d?, pte3/d+ rst , irq others v in v ss ? 1.0 to v dd +0.3 v ss ? 0.3 to v dd +0.3 v ss ? 0.3 to v reg +0.3 v mode entry voltage, irq pin v dd +v hi v ss ?0.3 to +11 v maximum current per pin excluding v dd and v ss i 25 ma storage temperature t stg ?55 to +150 c maximum current of ptd0/1 (20-pin package) i ol ?25 to +50 ma maximum current out of v ss i mvss 100 ma maximum current into v dd i mvdd 100 ma f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . electrical specifications functional operating range mc68hc908jb8mc68hc08jb8mc68HC08JT8 ? rev. 2.1 technical data motorola electrical specifications 255 18.4 functional operating range 18.5 thermal characteristics characteristic symbol value unit operating temperature range t a 0 to 70 c operating voltage range v dd 4.0 to 5.5 v characteristic symbol value unit thermal resistance qfp (44 pins) soic (28 pins) soic (20 pins) pdip (20 pins) ja 95 70 70 70 c/w i/o pin power dissipation p i/o user determined w power dissipation (1) notes: 1. power dissipation is a function of temperature. p d p d = (i dd v dd ) + p i/o = k/(t j + 273 c) w constant (2) 2. k is a constant unique to the device. k can be determined for a known t a and measured p d . with this value of k, p d and t j can be determined for any value of t a . k p d x (t a + 273 c ) + p d 2 ja w/ c average junction temperature t j t a + (p d ja ) c maximum junction temperature t jm 100 c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . electrical specifications technical data mc68hc908jb8mc68h c08jb8mc68HC08JT8 ? rev. 2.1 256 electrical specifications motorola 18.6 dc electrical characteristics characteristic (1) symbol min typ (2) max unit regulator output voltage v reg 3.0 3.3 3.6 v output high voltage (i load = ?2.0 ma) pta0?pta7, ptb0?ptb7, ptc0?ptc7, pte0?pte2 v oh v reg ?0.8 ??v output low voltage (i load = 1.6 ma) all i/o pins (i load = 25 ma) ptd0?ptd1 in ildd mode (i load = 10 ma) pte3?pte4 with usb disabled v ol ? ? ? ? ? ? 0.4 0.5 0.4 v input high voltage all ports, osc1 irq , rst v ih 0.7 v reg 0.7 v dd ? ? v reg v dd v input low voltage all ports, osc1 irq , rst v il v ss v ss ? ? 0.3 v reg 0.3 v dd v output low current (v ol = 2.0 v) ptd2?ptd5 in ldd mode i ol 10 13 20 ma v dd supply current, v dd = 5.25v, f op = 3mhz run, with low speed usb (3) run, with usb suspended (3) wait, with low speed usb (4) wait, with usb suspended (4) stop (5) 0 c to 70 c i dd ? ? ? ? ? 5.0 4.5 3.0 2.5 300 7.5 6.5 5.0 4.0 350 ma ma ma ma a i/o ports hi-z leakage current i il ?? 10 a input current i in ?? 1 a capacitance ports (as input or output) c out c in ? ? ? ? 12 8 pf por re-arm voltage (6) v por 0?100mv por rise-time ramp rate (7) r por 0.035 ? ? v/ms monitor mode entry voltage v dd + v hi 1.4 v dd ? 2 v dd v pullup resistors port a, port b, port c, pte0?pte2, rst , irq pte3?pte4 (with usb module disabled) d? (with usb module enabled) r pu 25 4 1.2 40 5 1.5 55 6 2 k ? lvi reset v lvr 2.8 3.3 3.8 v f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . electrical specifications control timing mc68hc908jb8mc68hc08jb8mc68HC08JT8 ? rev. 2.1 technical data motorola electrical specifications 257 18.7 control timing 18.8 oscillator characteristics notes: 1. v dd = 4.0 to 5.5 vdc, v ss = 0 vdc, t a = t l to t h , unless otherwise noted. 2. typical values reflect average measur ements at midpoint of voltage range, 25 c only. 3. run (operating) i dd measured using external square wave clock source (f xclk = 6 mhz). all inputs 0.2 v from rail. no dc loads. less than 100 pf on all outputs. c l = 20 pf on osc2. all ports configured as inputs. osc2 capacitance linearly affects run i dd . measured with all modules enabled. 4. wait i dd measured using external square wave clock source (f xclk = 6 mhz); all inputs 0.2 v from rail; no dc loads; less than 100 pf on all outputs. c l = 20 pf on osc2; 15 k ? 5% termination resistors on d+ and d? pins; all ports configured as inputs; osc2 capacitance linearly affects wait i dd 5. stop i dd measured with usb in suspend mode; osc1 gr ounded; transceiver pullup resistor of 1.5 k ? 5% between v reg and d? and 15 k ? 5% termination resistors on d+ and d? pins; no port pins sourcing current. 6. maximum is highest vo ltage that por is guaranteed. 7. if minimum v reg is not reached before the internal por reset is released, rst must be driven low externally until minimum v reg is reached. characteristic (1) notes: 1. v dd = 4.0 to 5.5 vdc; v ss = 0 vdc; timing shown with respect to 20% v dd and 70% v dd , unless otherwise noted. symbol min max unit internal operating frequency (2) 2. some modules may require a minimum frequency greater than dc for proper operation; see appropriate table for this infor- mation. f op ?3mhz rst input pulse width low (3) 3. minimum pulse width reset is guaranteed to be recognized. it is possible for a smaller pulse width to cause a reset. t irl 125 ? ns characteristic symbol min typ max unit crystal frequency (1) notes: 1. the usb module is designed to function at f xclk = 6 mhz. f xclk 1? 6 mhz external clock reference frequency (1), (2) 2. no more than 10% duty cycle deviation from 50%. f xclk dc ? 6 mhz crystal load capacitance (3) 3. consult crystal vendor data sheet. c l ?? ? crystal fixed capacitance (3) c 1 ? 2 c l ? crystal tuning capacitance (3) c 2 ? 2 c l ? feedback bias resistor r b ?10 m ? ? series resistor (3), (4) 4. not required for high-frequency crystals. r s ?? ? f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . electrical specifications technical data mc68hc908jb8mc68h c08jb8mc68HC08JT8 ? rev. 2.1 258 electrical specifications motorola 18.9 usb dc electrical characteristics characteristic (1) notes: 1. v dd = 4.0 to 5.5 vdc, v ss = 0 vdc, t a = t l to t h , unless otherwise noted. symbol conditions min typ max unit hi-z state data line leakage i lo 0 v electrical specifications technical data mc68hc908jb8mc68h c08jb8mc68HC08JT8 ? rev. 2.1 260 electrical specifications motorola 18.11 usb signaling levels 18.12 timer interface module characteristics bus state signaling levels transmit receive differential 1 d+ > v oh (min) and d? < v ol (max) (d+) ? (d?) > 200 mv differential 0 d? > v oh (min) and d? < v ol (max) (d?) ? (d+) > 200 mv single-ended 0 (se0) d+ and d? < v ol (max) d+ and d? < v il (max) data j state (low speed) dif ferential 0 differential 0 data k state (low speed) differential 1 differential 1 idle state (low speed) na d? > v ihz (min) and d+ < v il (max) resume state differential 1 differential 1 start of packet (sop) data lines switch from idle to k state end of packet (eop) se0 for approximately 2 bit times (1) followed by a j state for 1 bit time notes: 1. the width of eop is defined in bit time s relative to the speed of transmission. se0 for 1 bit time (2) followed by a j state for 1 bit time 2. the width of eop is defined in bit times relative to the device type receiving the eop. the bit time is approximate. reset na d+ and d? < v il (max) for 8 s characteristic symbol min max unit input capture pulse width t tih, t til 1/f op ? input clock pulse width t tch, t tcl (1/f op ) + 5ns ? f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . electrical specifications memory characteristics mc68hc908jb8mc68hc08jb8mc68HC08JT8 ? rev. 2.1 technical data motorola electrical specifications 261 18.13 memory characteristics characteristic symbol min max unit ram data retention voltage v rdr 1.3 ? v flash block size ? 512 bytes flash programming size ? 64 bytes flash read bus clock frequency f read (1) notes: 1. f read is defined as the frequency range for which the flash memory can be read. 32 k 8.4 m hz flash block erase time t erase (2) 2. if the page erase time is longer than t erase (min), there is no erase-disturb, but it reduced the endurance of the flash memory 2?ms flash mass erase time t merase (3) 3. if the mass erase time is longer than t merase (min), there is no erase-disturb, but it reduced the endurance of the flash mem- ory 2?ms flash pgm/erase to hven set up time t nvs 5? s flash high-voltage hold time t nvh 5? s flash high-voltage hold time (mass erase) t nvhl 100 ? s flash program hold time t pgs 10 ? s flash program time t prog 20 ? s flash return to read time t rcv (4) 4. t rcv is defined as the time it need before start the read of the flash after turn off the hven bit 1? s flash cumulative program hv period t hv (5) 5. t hv is defined as the cumulative high voltage programming time to the same row before next erase ?25ms flash row erase endurance (6) 6. the minimum row endurance value specifies each row of the flash memory is guaranteed to work for at least this many erase / program cycles. ?10k?cycles flash row program endurance (7) 7. the minimum row endurance value specifies each row of the flash memory is guaranteed to work for at least this many erase / program cycles. ?10k?cycles flash data retention time (8) 8. the flash is guaranteed to retain data over the entire operating temperature range for at least the minimum time specified. ?10?years f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . electrical specifications technical data mc68hc908jb8mc68h c08jb8mc68HC08JT8 ? rev. 2.1 262 electrical specifications motorola f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc908jb8mc68hc08jb8mc68HC08JT8 ? rev. 2.1 technical data motorola mechanical specifications 263 technical data ? mc68hc908jb8?mc68hc08jb8?mc68HC08JT8 section 19. mechanical specifications 19.1 contents 19.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 19.3 44-pin plastic quad flat pack (qfp) . . . . . . . . . . . . . . . . . . . 264 19.4 28-pin small outline in tegrated circuit (soic) . . . . . . . . . . . 265 19.5 20-pin dual in-line pa ckage (pdip) . . . . . . . . . . . . . . . . . . . 265 19.6 20-pin small outline in tegrated circuit (soic) . . . . . . . . . . . 266 19.2 introduction this section gives t he dimensions for: 44-pin plastic quad flat pack (case 824a) 28-pin small outli ne integrated circuit package (case 751f) 20-pin plastic dual in -line package (case 738) 20-pin small outli ne integrated circuit package (case 751d) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mechanical specifications technical data mc68hc908jb8mc68h c08jb8mc68HC08JT8 ? rev. 2.1 264 mechanical specifications motorola 19.3 44-pin plastic quad flat pack (qfp) figure 19-1. 44-pin qfp (case 824a) notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. datum plane ?h? is located at bottom of lead and is coincident with the lead where the lead exits the plastic body at the bottom of the parting line. 4. datums ?a?, ?b? and ?d? to be determined at datum plane ?h?. 5. dimensions s and v to be determined at seating plane ?c?. 6. dimensions a and b do not include mold protrusion. allowable protrusion is 0.25 (0.010) per side. dimensions a and b do include mold mismatch and are determined at datum plane ?h?. 7. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.08 (0.003) total in excess of the d dimension at maximum material condition. dambar cannot be located on the lower radius or the foot. l 33 34 23 22 44 111 12 detail a ?d? ?a? a s a?b m 0.20 (0.008) d s h s a?b m 0.20 (0.008) d s c 0.05 (0.002) a?b s b s a?b m 0.20 (0.008) d s h s a?b m 0.20 (0.008) d s c 0.05 (0.002) a?b v l ?b? ?c? seating plane m m e h g c ?h? datum plane detail c 0.10 (0.004) m ?h? datum plane t r k q w x detail c dim min max min max inches millimeters a 9.90 10.10 0.390 0.398 b 9.90 10.10 0.390 0.398 c 2.10 2.45 0.083 0.096 d 0.30 0.45 0.012 0.018 e 2.00 2.10 0.079 0.083 f 0.30 0.40 0.012 0.016 g 0.80 bsc 0.031 bsc h ? 0.25 ? 0.010 j 0.13 0.23 0.005 0.009 k 0.65 0.95 0.026 0.037 l 8.00 ref 0.315 ref m 5 10 5 10 n 0.13 0.17 0.005 0.007 q 0 7 0 7 r 0.13 0.30 0.005 0.012 s 12.95 13.45 0.510 0.530 t 0.13 ? 0.005 ? u 0 ?0 ? v 12.95 13.45 0.510 0.530 w 0.40 ? 0.016 ? x 1.6 ref 0.063 ref detail a b b ?a?, ?b?, ?d? s a?b m 0.20 (0.008) d s c f n section b?b j d base metal view rotated 90 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mechanical specifications 28-pin small outline in tegrated circuit (soic) mc68hc908jb8mc68hc08jb8mc68HC08JT8 ? rev. 2.1 technical data motorola mechanical specifications 265 19.4 28-pin small outline integrated circuit (soic) figure 19-2. 28-pin soic (case 751f) 19.5 20-pin dual in-line package (pdip) figure 19-3. 20-pin pdip (case 738) notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.13 (0.005) total in excess of d dimension at maximum material condition. j k f 1 15 14 28 -a- -b- 28x 14x d p s a m 0.010 (0.25) b s t m 0.010 (0.25) b m 26x g -t- seating plane c x 45 r m dim min max min max inches millimeters a 17.80 18.05 0.701 0.711 b 7.40 7.60 0.292 0.299 c 2.35 2.65 0.093 0.104 d 0.35 0.49 0.014 0.019 f 0.41 0.90 0.016 0.035 g 1.27 bsc 0.050 bsc j 0.23 0.32 0.009 0.013 k 0.13 0.29 0.005 0.011 m p 10.01 10.55 0.395 0.415 r 0.25 0.75 0.010 0.029 0 0 8 8 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. dimension l to center of lead when formed parallel. 4. dimension b does not include mold flash. m l j 20 pl m b m 0.25 (0.010) t dim min max min max millimeters inches a 25.66 27.17 1.010 1.070 b 6.10 6.60 0.240 0.260 c 3.81 4.57 0.150 0.180 d 0.39 0.55 0.015 0.022 g 2.54 bsc 0.100 bsc j 0.21 0.38 0.008 0.015 k 2.80 3.55 0.110 0.140 l 7.62 bsc 0.300 bsc m 0 15 0 15 n 0.51 1.01 0.020 0.040 e 1.27 1.77 0.050 0.070 1 11 10 20 ?a? seating plane k n f g d 20 pl ?t? m a m 0.25 (0.010) t e b c f 1.27 bsc 0.050 bsc f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mechanical specifications technical data mc68hc908jb8mc68h c08jb8mc68HC08JT8 ? rev. 2.1 266 mechanical specifications motorola 19.6 20-pin small outline integrated circuit (soic) figure 19-4. 20-pin soic (case 751d) notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions a and b do not include mold protrusion. 4. maximum mold protrusion 0.150 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.13 (0.005) total in excess of d dimension at maximum material condition. ?a? ?b? 20 1 11 10 s a m 0.010 (0.25) b s t d 20x m b m 0.010 (0.25) p 10x j f g 18x k c ?t? seating plane m r x 45 dim min max min max inches millimeters a 12.65 12.95 0.499 0.510 b 7.40 7.60 0.292 0.299 c 2.35 2.65 0.093 0.104 d 0.35 0.49 0.014 0.019 f 0.50 0.90 0.020 0.035 g 1.27 bsc 0.050 bsc j 0.25 0.32 0.010 0.012 k 0.10 0.25 0.004 0.009 m 0 7 0 7 p 10.05 10.55 0.395 0.415 r 0.25 0.75 0.010 0.029 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc908jb8mc68hc08jb8mc68HC08JT8 ? rev. 2.1 technical data motorola ordering information 267 technical data ? mc68hc908jb8?mc68hc08jb8?mc68HC08JT8 section 20. ordering information 20.1 contents 20.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267 20.3 mc order numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267 20.2 introduction this section contains ordering numbers for the mc68hc908jb8. 20.3 mc order numbers table 20-1. mc order numbers mc order number package operating temperature range mc68hc908jb8jp 20-pin pdip 0 c to +70 c mc68hc908jb8jdw 20-pin soic 0 c to +70 c mc68hc908jb8adw 28-pin soic 0 c to +70 c mc68hc908jb8fb 44-pin qfp 0 c to +70 c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . ordering information technical data mc68hc908jb8mc68h c08jb8mc68HC08JT8 ? rev. 2.1 268 ordering information motorola f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc908jb8mc68hc08jb8mc68HC08JT8 ? rev. 2.1 technical data motorola mc68hc08jb8 269 technical data ? mc68hc908jb8?mc68hc08jb8?mc68HC08JT8 appendix a. mc68hc08jb8 a.1 contents a.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270 a.3 mcu block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270 a.4 memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270 a.5 reserved registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273 a.6 monitor rom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .273 a.7 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273 a.7.1 dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . .274 a.7.2 memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 275 a.8 mc68hc08jb8 order numb ers . . . . . . . . . . . . . . . . . . . . . . . 275 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc08jb8 technical data mc68hc908jb8mc68h c08jb8mc68HC08JT8 ? rev. 2.1 270 mc68hc08jb8 motorola a.2 introduction this section introduces the mc68hc 08jb8, the rom part equivalent to the mc68hc908jb8. the entire data book apply to this rom device, with exceptions out lined in this appendix. a.3 mcu block diagram figure a-1 shows the block diagram of the mc68hc08jb8. a.4 memory map the mc68hc08jb8 has 8,192 bytes of user rom from $dc00 to $fbff, and 16 bytes of us er rom vectors from $fff0 to $ffff. on the mc68hc908jb8, these memory lo cations are flash memory. figure a-2 shows the memory ma p of the mc68hc08jb8. table a-1. summary of mc68hc 08jb8 and mc68hc 908jb8 differences mc68hc08jb8 mc68hc908jb8 memory ($dc00?$fbff) 8,192 bytes rom 8,192 bytes flash user vectors ($fff0?$ffff) 16 bytes rom 16 bytes flash registers at $fe08 and $ff09 not used; locations are reserved. flash related registers. $fe08 ? flcr $ff09 ? flbpr monitor rom ($fc00?$fdff and $fe10?$ffdf) $fc00?$fdff: not used. $fe10?$ffdf: used for testing purposes only. used for testing and flash programming/erasing. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc908jb8mc68hc08jb8mc68HC08JT8 ? rev. 2.1 technical data motorola mc68hc08jb8 271 mc68hc08jb8 figure a-1. mc68h c08jb8 block diagram system integration module timer interface module low voltage inhibit module computer operating properly module arithmetic/logic unit (alu) cpu registers m68hc08 cpu control and status registers ? 64 bytes user rom ? 8,192 bytes user ram ? 256 bytes monitor rom ? 464 bytes user rom vectors ? 16 bytes irq module power pta ddra ddre pte internal bus osc1 osc2 (1), (2) rst (1), (3) irq v dd v ss pta7/kba7 (3) pte4/d? (3) (4) (5) pte3/d+ (3) (4) (5) pte2/tch1 (3) pte1/tch0 (3) pte0/tclk (3) ptb ddrb ptb7?ptb0 (3) ptd ddrd ptd5?ptd2 (4) (5) usb module usb endpoint 0, 1, 2 internal voltage regulator v reg (3.3 v) (1) pins have 5v logic. (2) pins have integrated pullup device. (3) pins have software c onfigurable pull-up device. (4) pins are open-drain when configured as output. (5) pins have 10ma sink capability. (6) pins have 25ma sink capability. ls usb transceiver break module oscillator ptc ddrc ptc7?ptc0 (3) keyboard interrupt module power-on reset module ptd7?ptd6 (4) ptd1?ptd0 (4) (6) pta0/kba0 (3) : shaded blocks indicate differences to mc68hc908jb8 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc08jb8 technical data mc68hc908jb8mc68h c08jb8mc68HC08JT8 ? rev. 2.1 272 mc68hc08jb8 motorola $0000 $003f i/o registers 64 bytes $0040 $013f ram 256 bytes $0140 $dbff unimplemented 56,000 bytes $dc00 $fbff rom 8,192 bytes $fc00 $fdff unimplemented 512 bytes $fe00 break status register (bsr) $fe01 reset status register (rsr) $fe02 reserved $fe03 break flag control register (bfcr) $fe04 interrupt status register 1 (int1) $fe05 reserved $fe06 reserved $fe07 reserved $fe08 reserved $fe09 reserved $fe0a reserved $fe0b reserved $fe0c break address high register (brkh) $fe0d break address low register (brkl) $fe0e break status and control register (brkscr) $fe0f reserved $fe10 $ffdf monitor rom 464 bytes $ffe0 $ffef reserved 16 bytes $fff0 $ffff rom vectors 16 bytes figure a-2. mc68hc08jb8 memory map f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc08jb8 mc68hc908jb8mc68hc08jb8mc68HC08JT8 ? rev. 2.1 technical data motorola mc68hc08jb8 273 a.5 reserved registers the two registers at $fe 08 and $fe09 are rese rved locations on the mc68hc08jb8. on the mc68hc908jb8, these two locations ar e the flash control register and the flash block protect regi ster respectively. a.6 monitor rom the monitor program (monito r rom: $fe10?$ffdf) on the mc68hc08jb8 is for device test ing only. $fc00?$f dff are unused. a.7 electrical specifications electrical specifications for the mc68hc908jb8 apply to the mc68hc08jb8, except for the parameters i ndicated below. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc08jb8 technical data mc68hc908jb8mc68h c08jb8mc68HC08JT8 ? rev. 2.1 274 mc68hc08jb8 motorola a.7.1 dc electrical characteristics characteristic (1) symbol min typ (2) max unit regulator output voltage v reg 3.0 3.3 3.6 v output high voltage (i load = ?2.0 ma) pta0?pta7, ptb0?ptb7, ptc0?ptc7, pte0?pte2 v oh v reg ?0.8 ??v output low voltage (i load = 1.6 ma) all i/o pins (i load = 25 ma) ptd0?ptd1 in ildd mode (i load = 10 ma) pte3?pte4 with usb disabled v ol ? ? ? ? ? ? 0.4 0.5 0.4 v input high voltage all ports, osc1 irq , rst v ih 0.7 v reg 0.7 v dd ? ? v reg v dd v input low voltage all ports, osc1 irq , rst v il v ss v ss ? ? 0.3 v reg 0.3 v dd v output low current (v ol = 2.0 v) ptd2?ptd5 in ldd mode i ol 17 22 27 ma v dd supply current, v dd = 5.25v, f op = 3mhz run, with low speed usb (3) run, with usb suspended (3) wait, with low speed usb (4) wait, with usb suspended (4) stop (5) 0 c to 70 c i dd ? ? ? ? ? 5.0 4.5 3.0 2.5 30 7.5 6.5 5.0 4.0 100 ma ma ma ma a i/o ports hi-z leakage current i il ?? 10 a input current i in ?? 1 a capacitance ports (as input or output) c out c in ? ? ? ? 12 8 pf por re-arm voltage (6) v por 0?100mv por rise-time ramp rate (7) r por 0.035 ? ? v/ms monitor mode entry voltage v dd + v hi 1.4 v dd 2 v dd v pullup resistors port a, port b, port c, pte0?pte2, rst , irq pte3?pte4 (with usb module disabled) d? (with usb module enabled) r pu 25 4 1.2 40 5 1.5 55 6 2.0 k ? lvi reset v lvr 2.4 2.7 3.0 v f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc08jb8 mc68hc908jb8mc68hc08jb8mc68HC08JT8 ? rev. 2.1 technical data motorola mc68hc08jb8 275 a.7.2 memory characteristics a.8 mc68hc08jb8 order numbers these part numbers are generic number s only. to place an order, rom code must be submitted to the rom processing center (rpc). notes: 1. v dd = 4.0 to 5.5 vdc, v ss = 0 vdc, t a = t l to t h , unless otherwise noted. 2. typical values reflect average measur ements at midpoint of voltage range, 25 c only. 3. run (operating) i dd measured using external square wave clock source (f xclk = 6 mhz). all inputs 0.2 v from rail. no dc loads. less than 100 pf on all outputs. c l = 20 pf on osc2. all ports configured as inputs. osc2 capacitance linearly affects run i dd . measured with all modules enabled. 4. wait i dd measured using external square wave clock source (f xclk = 6 mhz); all inputs 0.2 v from rail; no dc loads; less than 100 pf on all outputs. c l = 20 pf on osc2; 15 k ? 5% termination resistors on d+ and d? pins; all ports configured as inputs; osc2 capacitance linearly affects wait i dd 5. stop i dd measured with usb in suspend mode; osc1 gr ounded; transceiver pullup resistor of 1.5 k ? 5% between v reg and d? pins and 15 k ? 5% termination resistor on d+ pin; no port pins sourcing current. 6. maximum is highest vo ltage that por is guaranteed. 7. if minimum v reg is not reached before the internal por reset is released, rst must be driven low externally until minimum v reg is reached. characteristic symbol min max unit ram data retention voltage v rdr 1.3 ? v notes: since mc68hc08jb8 is a rom device, flash memory electrical characteristics do not apply. table a-2. mc68hc08jb8 order numbers mc order number package operating temperature range mc68hc08jb8jp 20-pin pdip 0 c to +70 c mc68hc08jb8jdw 20-pin soic 0 c to +70 c mc68hc08jb8adw 28-pin soic 0 c to +70 c mc68hc08jb8fb 44-pin qfp 0 c to +70 c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc08jb8 technical data mc68hc908jb8mc68h c08jb8mc68HC08JT8 ? rev. 2.1 276 mc68hc08jb8 motorola f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc908jb8mc68hc08jb8mc68HC08JT8 ? rev. 2.1 technical data motorola mc68HC08JT8 277 technical data ? mc68hc908jb8?mc68hc08jb8?mc68HC08JT8 appendix b. mc68HC08JT8 b.1 contents b.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278 b.3 mcu block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278 b.4 memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278 b.5 power supply pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281 b.6 reserved register bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281 b.7 reserved registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281 b.8 monitor rom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .282 b.9 universal serial bus module. . . . . . . . . . . . . . . . . . . . . . . . . . 282 b.10 low-voltage inhibit module . . . . . . . . . . . . . . . . . . . . . . . . . . 282 b.11 electrical specific ations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282 b.11.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . 282 b.11.2 functional operating range . . . . . . . . . . . . . . . . . . . . . . .283 b.11.3 dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . .283 b.11.4 control timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284 b.11.5 memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 284 b.12 mc68HC08JT8 order number s . . . . . . . . . . . . . . . . . . . . . . . 284 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68HC08JT8 technical data mc68hc908jb8mc68h c08jb8mc68HC08JT8 ? rev. 2.1 278 mc68HC08JT8 motorola b.2 introduction this section introduces the mc68h c08jt8, a low-voltage rom part version to the mc68hc908jb8. the ent ire data book apply to this rom device, with exceptions outlined in this appendix. b.3 mcu block diagram figure b-1 shows the block diagr am of the mc68HC08JT8. b.4 memory map the mc68HC08JT8 has 8,192 bytes of user rom from $dc00 to $fbff, and 16 bytes of us er rom vectors from $fff0 to $ffff. on the mc68hc908jb8, these memory lo cations are flash memory. figure b-2 shows the memory ma p of the mc68HC08JT8. table b-1. summary of mc68hc 08jt8 and mc68hc 908jb8 differences mc68HC08JT8 mc68hc908jb8 memory ($dc00?$fbff) 8,192 bytes rom 8,192 bytes flash user vectors ($fff0?$ffff) 16 bytes rom 16 bytes flash registers at $fe08 and $ff09 not used; locations are reserved flash related registers. $fe08 ? flcr $ff09 ? flbpr bit 4 at config ($001f) not used; bit is reserved. lvid: low-voltage inhibit disable bit monitor rom ($fc00?$fdff and $fe10?$ffdf) $fc00?$fdff: not used. $fe10?$ffdf: used for testing purposes only. used for testing and flash programming/erasing. low voltage inhibit module not available (disabled) available universal serial bus (usb) module not available. user should set the suspnd bit to logic 1 to reduce power consumption. available on-chip 3.3v regulator not available (disabled) available operating voltage 2.0 to 3.6v 4.0 to 5.5v operating frequency f opmax = 2.5mhz at 2v f opmax = 3mhz at 3v 3mhz f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68hc908jb8mc68hc08jb8mc68HC08JT8 ? rev. 2.1 technical data motorola mc68HC08JT8 279 mc68HC08JT8 figure b-1. mc68HC08JT8 block diagram system integration module timer interface module low voltage inhibit module computer operating properly module arithmetic/logic unit (alu) cpu registers m68hc08 cpu control and status registers ? 64 bytes user rom ? 8,192 bytes user ram ? 256 bytes monitor rom ? 464 bytes user rom vectors ? 16 bytes irq module power pta ddra ddre pte internal bus osc1 osc2 (1), (2) rst (1), (3) irq v dd v ss pta7/kba7 (3) pte4 (3) (4) (5) pte3 (3) (4) (5) pte2/tch1 (3) pte1/tch0 (3) pte0/tclk (3) ptb ddrb ptb7?ptb0 (3) ptd ddrd ptd5?ptd2 (4) (5) usb module usb endpoint 0, 1, 2 internal voltage regulator v reg (3.3 v) (1) pins have 5v logic. (2) pins have integrated pullup device. (3) pins have software c onfigurable pull-up device. (4) pins are open-drain when configured as output. (5) pins have 10ma sink capability. (6) pins have 25ma sink capability. ls usb transceiver break module oscillator ptc ddrc ptc7?ptc0 (3) keyboard interrupt module power-on reset module ptd7?ptd6 (4) ptd1?ptd0 (4) (6) pta0/kba0 (3) : shaded blocks indicate differences to mc68hc908jb8 disabled disabled not available f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68HC08JT8 technical data mc68hc908jb8?mc68h c08jb8mc68HC08JT8 ? rev. 2.1 280 mc68HC08JT8 motorola $0000 $003f i/o registers 64 bytes $0040 $013f ram 256 bytes $0140 $dbff unimplemented 56,000 bytes $dc00 $fbff rom 8,192 bytes $fc00 $fdff unimplemented 512 bytes $fe00 break status register (bsr) $fe01 reset status register (rsr) $fe02 reserved $fe03 break flag control register (bfcr) $fe04 interrupt status register 1 (int1) $fe05 reserved $fe06 reserved $fe07 reserved $fe08 reserved $fe09 reserved $fe0a reserved $fe0b reserved $fe0c break address high register (brkh) $fe0d break address low register (brkl) $fe0e break status and control register (brkscr) $fe0f reserved $fe10 $ffdf monitor rom 464 bytes $ffe0 $ffef reserved 16 bytes $fff0 $ffff rom vectors 16 bytes figure b-2. mc68h c08jt8 memory map f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68HC08JT8 mc68hc908jb8mc68hc08jb8mc68HC08JT8 ? rev. 2.1 technical data motorola mc68HC08JT8 281 b.5 power supply pins the mc68HC08JT8 is design for low voltage operation. connect v dd and v reg for normal operation. the v reg voltage regulator is di sabled on the mc68HC08JT8. figure b-3. power supply bypassing b.6 reserved register bit bit 4 of the configuration regist er ($001f) is a reserved bit on the mc68HC08JT8. the bit will always read as zero. on the mc68hc908jb8, bi t 4 of the configurati on register is the low- voltage inhibit disable bit, lvid. b.7 reserved registers the two registers at $fe 08 and $fe09 are rese rved locations on the mc68HC08JT8. on the mc68hc908jb8, these two locations ar e the flash control register and the flash block protect regi ster respectively. mcu c bulk 10 f c bypass 0.1 f + note: values shown are typical values. v dd v reg v ss v dd f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68HC08JT8 technical data mc68hc908jb8mc68h c08jb8mc68HC08JT8 ? rev. 2.1 282 mc68HC08JT8 motorola b.8 monitor rom the monitor program (monito r rom: $fe10?$ffdf) on the mc68HC08JT8 is for device te sting only. $fc 00?$fdff are unused. b.9 universal serial bus module the usb module is designed for operation with v dd = 4v to 5.5v, therefore, it should not be used on the mc68HC08JT8 device. to further reduce current consumpt ion in stop mode, set the suspnd bit in the usb interrupt register 0 (uir0) to lo gic 1. other usb registers should be left in their default state. b.10 low-voltage inhibit module the lvi module is disabl ed on the mc68HC08JT8. b.11 electrical specifications electrical specifications for the mc68hc908jb8 apply to the mc68HC08JT8, except for the parameters indicated below. b.11.1 absolute maximum ratings characteristic (1) notes: 1. voltages referenced to v ss . symbol value unit supply voltage v dd ?0.3 to +3.9 v input voltage v in v ss ? 0.3 to v dd +0.3 v maximum current per pin excluding v dd and v ss i 25 ma storage temperature t stg ?55 to +150 c maximum current of ptd0/1 (20-pin package) i ol ?15 to +30 ma maximum current out of v ss i mvss 100 ma maximum current into v dd i mvdd 100 ma f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68HC08JT8 mc68hc908jb8mc68hc08jb8mc68HC08JT8 ? rev. 2.1 technical data motorola mc68HC08JT8 283 b.11.2 functional operating range b.11.3 dc electrical characteristics characteristic symbol value unit operating temperature range t a 0 to 70 c operating voltage range v dd 2.0 to 3.6 v characteristic (1) symbol min typ (2) max unit output high voltage (i load = ?1.6 ma) pta0?pta7, ptb0?ptb7, ptc0?ptc7, pte0?pte2 v oh v dd ?0.4 ??v output low voltage (i load = 1.6 ma) all i/o pins (i load = 15 ma) ptd0?ptd1 in ildd mode (i load = 5 ma) pte3?pte4 v ol ? ? ? ? ? ? 0.4 0.5 0.4 v input high voltage all ports, osc1, irq , rst v ih 0.7 v dd ? v dd v input low voltage all ports, osc1, irq , rst v il v ss ? 0.3 v dd v output low current (v ol = 2.0 v) (3) ptd2?ptd5 in ldd mode (v dd = 2v) ptd2?ptd5 in ldd mode (v dd = 3v) i ol ? ? 6 16 ? ? ma v dd supply current, v dd = 3v, f op = 3mhz run (4) wait (5) stop (6) 0 c to 70 c i dd ? ? ? 3.5 2.5 20 6.5 4.5 30 ma ma a i/o ports hi-z leakage current i il ?? 10 a input current i in ?? 1 a capacitance ports (as input or output) c out c in ? ? ? ? 12 8 pf por re-arm voltage (7) v por 0?100mv por rise-time ramp rate r por 0.02 ? ? v/ms monitor mode entry voltage v dd + v hi 1.4 v dd 2 v dd v pullup resistors port a, port b, port c, pte0?pte2, rst , irq pte3?pte4 r pu 25 4 40 5 55 6 k ? k ? f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68HC08JT8 technical data mc68hc908jb8mc68h c08jb8mc68HC08JT8 ? rev. 2.1 284 mc68HC08JT8 motorola b.11.4 control timing b.11.5 memory characteristics b.12 mc68HC08JT8 order numbers these part numbers are generic number s only. to place an order, rom code must be submitted to the rom processing center (rpc). notes: 1. v dd = 2.0 to 3.6 vdc, v ss = 0 vdc, t a = t l to t h , unless otherwise noted. 2. typical values reflect average measurements at 3v, 25 c only. 3. in ldd mode, the specified i ol is achieved when the external pullup voltage is equal to or higher than the voltage: v ol + voltage dropped across led. 4. run (operating) i dd measured using external square wave clock source (f xclk = 6 mhz). all inputs 0.2 v from rail. no dc loads. less than 100 pf on all outputs. c l = 20 pf on osc2. all ports configured as inputs. osc2 capacitance linearly affects run i dd . measured with all modules enabled. 5. wait i dd measured using external square wave clock source (f xclk = 6 mhz). all inputs 0.2 v from rail. no dc loads. less than 100 pf on all outputs. c l = 20 pf on osc2. all ports configured as i nputs. osc2 capacitance linearly affects wait i dd . 6. stop i dd measured with osc1 grounded; no port pins sourcing current. 7. maximum is highest vo ltage that por is guaranteed. characteristic symbol min max unit internal operating frequency v dd = 2.0v v dd = 3.0v f op ? ? 2.5 3.0 mhz mhz characteristic symbol min max unit ram data retention voltage v rdr 1.3 ? v notes: since mc68HC08JT8 is a rom device, flash memory electrical characteristics do not apply. table b-2. mc68HC08JT8 order numbers mc order number package operating temperature range mc68HC08JT8jdw 20-pin soic 0 c to +70 c mc68HC08JT8fb 44-pin qfp 0 c to +70 c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . how to reach us: usa/europe/locations not listed: motorola literature distribution p.o. box 5405 denver, colorado 80217 1-800-521-6274 or 480-768-2130 japan: motorola japan ltd. sps, technical information center 3-20-1, minami-azabu, minato-ku tokyo 106-8573, japan 81-3-3440-3569 asia/pacific: motorola semiconductors h.k. ltd. silicon harbour centre 2 dai king street tai po industrial estate tai po, n.t., hong kong 852-26668334 home page: http://motorola.com/semiconductors mc68hc908jb8/d rev. 2.1 12/2003 information in this document is provided solely to enable system and software implementers to use motorola products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. motorola reserves the right to make changes without further notice to any products herein. motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability , including without limitation consequential or incidental damages. ?typical? parameters that may be provided in motorola data sheets and/or specifications can and do vary in differen t applications and actual performance may vary over time. all operating parameters, including ?typicals?, must be validated for each customer application by customer?s technical experts. motorola does not convey any license under its patent rights nor the rights of others. motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the motorola product could create a situation where personal injury or death may occur. should buyer purchase or use motorola products for any such unintended or unauthorized application, buyer shall indemnify and hold motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that motorola was negligent regarding the design or manufacture of the part. motorola and the stylized m logo are registered in the us patent and trademark office. all other product or service names are the property of their respective owners. motorola, inc. is an equal opportunity/affirmative action employer. ? motorola inc. 2003 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . |
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